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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 115/144頁 |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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5.8.11
Transmit Frame Length
The length of the frame transmitted is deter-
mined by the value written into the TxLength
register (PacketPage base + 0146h) during the
Transmit Request. The length of the transmit
frame may be modified by the configuration of
the TxPadDis bit (Register 9, TxCMD, Bit D)
and the InhibitCRC bit (Register 9, TxCMD, Bit
C). Table 5.17 defines how these bits affect the
length of the transmit frame. In addition, it
shows which frames the CS8920A will send.
5.9
Full Duplex Considerations
The driver should not bid to transmit a long
frame (i.e., a frame greater than 118 bytes) if the
prior transmit frame is still being transmitted.
The end of the transmission of this prior frame is
indicated by a TxOK bit being set in the
TxEvent register (register 8).
5.10
Frames
System Wakeup with Wakeup
The CS8920A will recognize a Magic Packet
wakeup frame that is received from either the
10BASE-T or AUI port, and can consequently
generate a signal to awaken a sleeping or idling
system CPU. A desktop system may go to sleep
in response to any number of conditions. For ex-
ample, a system power manager observes no user
or computing activity for some period of time, or
a user turns the PC off using a soft or hard
power switch.
Wakeup frame recognition allows access to a
sleeping (powered-down or slowed down) CPU
over the network. Potential applications include
personal remote access to a desktop PC, or ac-
cess by a host to all clients to upgrade software
programs, perform virus scans, or check for un-
authorized software.
A complete wakeup frame state diagram is
shown in Figure 5.14. The key states are as fol-
lows:
NORMAL: The CS8920A is receiving nor-
mal packet traffic and is ignoring wakeup
frames.
SUSPEND: The CS8920A is waiting for a
wakeup frame and is ignoring all other
frames. The ISA bus is powered down. Typi-
cally, the CPU is also powered down.
STANDBY: The CS8920A is waiting for a
wakeup frame and is ignoring all other
frames. The ISA bus is powered up, and typi-
cally the CPU is running with a slowed-down
clock.
RESET: The CS8920A is performing an in-
ternal reset and all received frames are
ignored. The state entered following RESET
is determined by the contents of the
EEPROM and by whether or not the ISA bus
is powered up.
DROPPING FRAME: The CS8920A is look-
ing for normal packet traffic, but the ISA bus
is not powered up. This is a somewhat abnor-
mal condition.
Wakeup Frame Control/Status Bits
The following Control/Status bits are associated
with the wakeup function.
LineCTL (Register 13)
bit F, WakeupEN: Set this bit to enable the
wakeup function. All non-wakeup frames are
discarded when wakeup is enabled. This bit
defaults to clear, meaning wakeup frame rec-
ognition is disabled. When recognition is
disabled, the EWAKE pin remains low inde-
pendent of the state of LineCTL, bit A.
CS8920A
DS238PP2
115
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