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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 45/144頁 |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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4.4
Status and Control Registers
The Status and Control registers are the primary
registers used to control and check the status of
the CS8920A. They are organized into two
groups: Configuration/Control Registers and
Status/Event Registers. All Status and Control
Registers are 16-bit words as shown in Figure
4.1. Bit 0 indicates whether it is a Configura-
tion/Control Register (Bit 0 = 1) or a
Status/Event Register (Bit 0 = 0). Bits 0 through
5 provide an internal address code that describes
the exact function of the register. Bits 6 through
F are the actual Configuration/Control and
Status/Event bits.
Configuration and Control Registers
Configuration and Control registers are used to
set up the following:
how frames will be transmitted and received;
which frames will be transmitted and re-
ceived;
which events will cause interrupts to the
host processor; and,
how the Ethernet physical interface will be
configured.
These registers are read/write and are designated
by odd numbers (e.g. Register 1, Register 3,
etc.).
The Transmit Command Register (TxCMD) is a
special type of register. It appears in two separate
locations in the PacketPage memory map. The
first location, PacketPage base + 0108h, is within
the Configuration/Control Register block and is
read-only. The second location, PacketPage base
+ 0144h, is where the actual transmit commands
are issued and is write-only. See Section 4.4
(Register 9) and Section 5.8 for a more detailed
description of the TxCMD register.
Status and Event Registers
Status and Event registers report the status of
transmitted and received frames, as well as infor-
mation about the configuration of the CS8920A.
They are read-only and are designated by even
numbers (e.g. Register 2, Register 4, etc.).
The Interrupt Status Queue (ISQ) is a special
type of Status/Event register. It is located at
PacketPage base + 0120h and is the first register
the host reads when responding to an Interrupt.
A more detailed description of the ISQ can be
found in Section 5.1.
1
0
3
2
5
4
7
6
10 Register Bits
Figure 4.1. Status and Control Register Format
1 = Control/Configuration
0 = Status/Event
Internal Address
(bits 0 - 5)
16-bit Register Word
Bit Number
9
8
B
A
D C
F
E
CS8920A
DS238PP2
45
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