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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 13/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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General Pins
Symbol
XTAL1
XTAL2
Pin Number
135
136
Type
I/O
Description
Crystal:
A 20 MHz crystal should be connected across these pins. If a
crystal is not used, a 20 MHz signal should be connected to XTAL1 and
XTAL2 should be left open. (See section 9.0 and 13.0.)
Hardware Sleep:
Active-low input used to enable the two hardware sleep
modes: Hardware Suspend and Hardware Standby. (See section 3.8.)
Wakeup Signal:
The CS8920A asserts EWAKE high when a wakeup
frame is detected on the Ethernet receiver.
OD10
Link Good LED or Host Controlled Output 0:
When the HCE0 bit of the
Self Control register (Register 15) is clear, this active-low output is low
when the CS8920A detects the presence of valid link pulses. When the
HCE0 bit is set, the host may drive this pin low by setting the HCBO in the
Self Control register.
OD10
Bus Status or Host Controlled Output 1:
When the HCE1 bit of the Self
Control register (Register 15) is clear, this active-low output is low when
receive activity causes an ISA bus access. When the HCE1 bit is set, the
host may drive this pin low by setting the HCB1 in the Self Control register.
OD10
LAN Activity LED:
During normal operation, this active-low output goes
low for 6 ms whenever there is a receive packet, a transmit packet, or a
collision. During Hardware Standby mode, this output is driven low when
the receiver detects network activity.
OD10
Local Activity LED:
During normal operation, this active-low output goes
low for 6 ms whenever there is either a receive packet addressed to this
node, or a transmit packet.
IW
Test Enable:
Active-low input used to put the CS8920A in Boundary Scan
Test mode. For normal operation, this pin should be high or left open.
I
Reference Resistor:
This input should be connected to a 4.99 K
+/-1%
resistor needed for biasing of internal analog circuits.
P
Digital Power:
Provides 5 V +/- 5% power to the digital circuits of the
CS8920A.
G
Digital Ground: Provides ground reference (0V) to the digital circuits of the
CS8920A.
Provide additional ground references (0V) to digital circuits of the CS8920A.
SLEEP
116
IW
EWAKE
3
O4w
LINKLED
or
HC0
139
BSTATUS
or
HC1
113
LANLED
140
LOCALLED
5
TEST
115
RES
131
DVDD1 -
DVDD5
DVSS1 -
DVSS5
DSUB1 -
DSUB3
AVDD1 -
AVDD3
AVSS1 -
AVSS7
12, 22,
55, 94, 101
11, 23, 56,
93, 100
13, 54,
95
133, 128,
123
4, 124, 127,
132, 134,
137, 138
4, 134,
137, 138
P
Analog Power: Provides 5 V +/- 5% power to the analog circuits of the
CS8920A.
Analog Ground: Provide ground reference (0V) to the analog circuits of the
CS8920A.
G
AVSS1 -
AVSS4
Pin Types:
dI
dO
B
OD
Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).
Provided additional ground references (0V) to analog circuits of the
CS8920A.
=
=
=
=
Differential Input Pair
Differential Output Pair
Bi-Directional with Tri-State Output P
Open Drain Output
I
=
=
=
Input
Output
Power
G
ts
w
=
=
=
Ground
Tri-State
Internal Weak Pullup
O
CS8920A
DS238PP2
13
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