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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 98/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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If
bit Hashed =0, or
bit RxOK=0, or
(bits F-A = 02h and the destination
address is all ones)
then RxEvent contains a normal RxEvent
else RxEvent contained a hash RxEvent.
5.4
Rx Missed and Tx Collision Counters
5.4.1
RxMiss counter
The RxMiss counter is (Register 10) incremented
when receive data are lost (missed) due to slow
movement of the data out of the receive buffer.
RxMiss is a ten-bit counter (bit 6 to bit F) with
bit 6 as the LSB. RxMiss is cleared when read.
When MissOvfloiE is (Register B, Buf CFG, bit
D) set, there is an interrupt when RxMiss incre-
ments from 1FFh to 200h. The actual overflow is
at 3FFh. Interrupting at 200h provides an addi-
tional 512 (decimal) counts before RxMiss
actually overflows back to 000h.
5.4.2
TxCOL counter
The TxCol counter (Register 12) is incremented
when there is a transmit collision. TxCOL is a
ten-bit counter (bit 6 to bit F) with bit 6 as the
LSB. TxCOL is cleared when read.
When TxColOvfiE (Register B, Buf CFG, bit C)
is set, there is an interrupt when RxMiss incre-
ments from 1FFh to 200h. The actual overflow is
at 3FFh. Interrupting at 200h provides an addi-
tional 512 (decimal) counts before TxCOL
actually overflows back to 000h.
5.5
Receive DMA
5.5.1
Overview
The CS8920A supports a direct interface to the
host DMA controller allowing it to transfer re-
ceive frames to host memory via slave DMA.
The DMA option applies only to receive frames,
not to transmit operation. The CS8920A offers
three possible Receive DMA modes:
1. Receive-DMA-only mode: All receive frames
are transferred via DMA.
2. Auto-Switch DMA mode: DMA is used only
when needed to help prevent missed frames.
3. StreamTransfer mode: DMA is used to mini-
mize the number of interrupts to the host.
This section provides a description of Receive-
DMA-only mode. Section 5.6 describes
Auto-Switch DMA and Section 5.7 describes
StreamTransfer.
5.5.2
Operation
Configuring the CS8920A for DMA
The CS8920A interfaces to the host DMA con-
troller through one pair of the DMA
request/acknowledge pins (see Section 3.2 for a
description of the CS8920A’s DMA interface).
Four registers are used for DMA operation.
These are described in Table 5.8.
Receive-DMA-only mode is enabled by setting
the RxDMAonly bit (Register 3, RxCFG, Bit 9).
Note that if the RxDMAonly bit and the
AutoRxDMAE bit (Register 3, RxCFG, Bit A)
are both set, then RxDMAonly takes precedence,
and the CS8920A is in DMA mode for all re-
ceive frames.
5.5.3
DMA Receive Buffer Size
In receive DMA mode, the CS8920A stores re-
ceived frames (along with their status and length)
in a circular buffer located in host memory
space. The size of the circular buffer is deter-
mined by the RxDMAsize bit (Register 17,
BusCTL, Bit D). When RxDMAsize is clear, the
CS8920A
98
DS238PP2
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