參數(shù)資料
型號(hào)： CDK8920A
廠(chǎng)商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁(yè)數(shù)： 110/144頁(yè)
文件大?。?/td> 1229K
代理商： CDK8920A
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the TxCMD register may be read back from
the TxCMD register (Register 9).
2. The host must write the frame’s length to the
TxLength register (PacketPage base + 0146h
or I/O base + 0006h).
3. The host must read the BusST register (Regis-
ter 18) to check Rdy4TxNow (bit 8).
The information written to the TxCMD register
tells the CS8920A how to transmit the next
frame. The bits that must be programmed in the
TxCMD register are described in Table 5.16.
For each individual packet transmission, the host
must issue a
complete
Transmit Request. Also,
the host must write to the TxCMD register be-
fore each packet transmission, even if the
contents of the TxCMD register do not change.
The Transmit Request may be in either Memory
Space or I/O Space, as described in sections
5.8.6 and 5.8.7.
Note for Rev B silicon, it is recommended that
the use TxStart of 01 (start preamble after 381
bytes have been transferred). For rev C and
later, any TxStart mode may be used.
5.8.6
Transmit in Poll Mode
In poll mode, Rdy4TxiE bit (Register B
“BufCFG”, Bit 8) must be clear (Interrupt Dis-
abled). The transmit operation occurs in the
following order and is shown in Figure 5.12
1. The host bids for frame storage by writing the
Transmit Command to the TxCMD register
(memory base+ 0144h in memory mode or
I/O base + 0004h in I/O mode).
2. The host writes the transmit frame length to the
TxLength register (memory base + 0146h in
memory mode or I/O base + 0006h in I/O
mode). If the transmit length is erroneous, the
command is discarded and the TxBidErr bit
(Register 18, BusST, Bit 7) is set.
3. The host reads the BusST register. This read is
performed in memory mode by reading Regis-
ter 18, at memory base + 0138h. In I/O
mode, the host must first set the PacketPage
Pointer at the correct location by writing
0138h to the PacketPage Pointer Port (I/O
base + 000Ah). The host can then read the
BusST register from the PacketPage Data Port
(I/O base + 000Ch).
After reading the register, the Rdy4TxNOW
bit (Bit 8) is checked. If the bit is set, the
frame can be written. If the bit is clear, the
host must continue reading the BusST register
(Register 18) and checking the Rdy4TxNOW
bit (Bit 8) until the bit is set.
When the CS8920A is ready to accept the frame,
the host transfers the entire frame from host
Register 9, TxCMD
Bit
Bit Name
Tx Start
Operation
7
0
6
0
Start preamble after 5 bytes have
been transferred to the CS8920A.
Start preamble after 381 bytes
have been transferred to the
CS8920A.
Start preamble after 1021 bytes
have been transferred to the
CS8920A.
Start preamble after entire frame
has been transferred to the
CS8920A.
When set, the CS8920A discards
any frame data currently in the
transmit buffer.
When set, the CS8920A will not
attempt to re-transmit any packet
after a collision.
InhibitCRC When set, the CS8920A does not
append the 32-bit CRC value to the
end of any transmit packet.
TxPadDis When set, the CS8920A will not
add pad bits to short frames.
0
1
1
0
1
1
8
Force
9
Onecoll
C
D
Table 5.16. Tx Command Configuration
CS8920A
110
DS238PP2
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