參數(shù)資料
型號： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁數(shù)： 61/144頁
文件大小： 1229K
代理商： CDK8920A
Register 12: Transmit Collision Counter (TxCOL, Read-only)
Address: PacketPage base + 0132h
F-6
5-0
ColCount
010010
The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or
AUI Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. When the TxColOvfiE bit
(Register B, BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This
interrupt provides the host with an early warning that the TxCOL counter should be read before it reaches 3FFh
and starts over (by interrupting at 200h, the host has an additional 512 counts before TxCOL actually overflows).
The TxCOL counter is cleared when read.
BIT
NAME
DESCRIPTION
5-0
010010
These bits provide an internal address used by the CS8920A to identify this as the
Bus Status Register. When reading this register, these bits will be 010010, where the
LSB corresponds to Bit 0.
F-6
ColCount
The upper ten bits contain the number of collisions.
This register’s initial state after reset is:
0000 0000
0001 0010
Register 10: Receiver Miss Counter (RxMISS, Read-only)
Address: PacketPage base + 0130h
F-6
5-0
MissCount
010000
The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the
lack of available buffer space. When the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt
when RxMISS increments from 1FFh to 200h. This interrupt provides the host with an early warning that the
RxMISS counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the host has an
additional 512 counts before RxMISS actually overflows). The RxMISS counter is cleared when read.
BIT
NAME
DESCRIPTION
5-0
010000
These bits provide an internal address used by the CS8920A to identify this as the
Bus Status Register. When reading this register, these bits will be 010000, where the
LSB corresponds to Bit 0.
F-6
MissCount
The upper ten bits contain the number of missed frames.
This register’s initial state after reset is:
0000 0000
0001 0000
CS8920A
DS238PP2
61
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