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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 26/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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To enter HW Standby mode, the SLEEP pin
must be low
and
the HWSleepE bit (Register 15,
SelfCTL, Bit 9)
and
the HWstandbyE bit (Regis-
ter 15, SelfCTL, Bit A) must be set. When the
CS8920A enters HW Standby, all registers and
circuits are reset except for the SelfCTL register.
Upon exit from HW Standby, the CS8920A per-
forms a complete reset, and then goes through
normal initialization.
Hardware Suspend
During Hardware Suspend mode, the CS8920A
uses the least amount of current of the three low-
power modes. All internal circuits are turned off
and the CS8920A’s core is electronically isolated
from the rest of the system. Accesses from the
ISA bus and Ethernet activity are both ignored.
HW Suspend mode is entered by driving the
SLEEP pin low and setting the HWSleepE bit
(Register 15, SelfCTL, bit 9) while the
HWstandbyE bit (Register 15, SelfCTL, bit A) is
clear. To exit from this mode, the SLEEP pin
must be driven high. Upon exit, the CS8920A
performs a complete reset, and then goes through
a normal initialization procedure.
Software Suspend
Software (SW) Suspend mode can be used to
conserve power in certain applications, such as
adapter cards that do not have power manage-
ment circuitry available. During software
suspend mode there is a partial reset. All regis-
ters and circuits are reset except for the Plug and
Play state, CSN, read data port, ISA I/O Base
Address Register, and the SelfCTL register.
To enter SW Suspend mode, the host must set
the SWSuspend bit (Register 15, SelfCTL, bit 8).
To exit SW Suspend, the host must write to the
CS8920A’s assigned I/O space (the write is only
used to wake the CS8920A, the write itself is
ignored). Upon exit, the CS8920A performs a
complete reset, then goes through a normal in-
itialization procedure.
Any hardware reset takes the chip out of any
sleep mode.
Table 3.8 summarizes the operation of the three
low-power modes.
3.9
LED Outputs
The CS8920A provides four output pins that can
be used to control LEDs or external logic.
LANLED:
LANLED goes low whenever the
CS8920A transmits or receives a frame, or when
it detects a collision. LANLED remains low until
there has been no activity for 6 ms (i.e. each
transmission, reception, or collision produces a
pulse lasting a minimum of 6 ms).
HC0E
(Bit C)
0
HCB0
(Bit E)
N/A
Pin Function
Pin configured as LINKLED: Output
is low when valid 10BASE-T link
pulses are detected. Output is high if
valid link pulses are not detected.
Pin configured as HC0:
Output is high
Pin configured as HC0:
Output is low
1
0
1
1
Table 3.9.
LINKLED/HC0 Pin Operation
HC1E
(Bit D)
0
HCB1
(Bit F)
N/A
Pin Function
Pin configured as BSTATUS: Output
is low when a receive frame begins
transfer across the ISA bus. Output is
high otherwise.
Pin configured as HC1:
Output is high
Pin configured as HC1:
Output is low
1
0
1
1
Table 3.10.
BSTATUS/HC1 Pin Operation
CS8920A
26
DS238PP2
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