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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 52/144頁 |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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Register 4: Receiver Event (RxEvent, Read-only)
Address: PacketPage base + 0124h
F
E
D
C
B
A
9
8
7
6
5-0
EWAKE
event
Alternate meaning if bits 8 and 9 are both set (see Section 5.3 for exception regarding Broadcast frames).
F
E
D
C
B
Hash Table Index (see Section 5.3)
Extradata
Runt
CRCerror
Broad
cast
Individual
Adr
Hashed
RxOK
Dribblebits
IAHash
000100
A
9
8
7
6
5-0
Hashed
= 1
RxOK = 1 Dribblebits
IAHash
000100
RxEvent reports the status of the current received frame. All RxEvent bits are cleared upon readout. The host is
responsible for processing all event bits. RxStatus register (PacketPage base + 0400h) is the same as the
RxEvent register except RxStatus is not cleared when RxEvent is read. See Section 5.2. Value in RxEvent
register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set.
BIT
NAME
DESCRIPTION
5-0
000100
These bits identify this as the Receiver Event Register. When reading this register,
these bits will be 000100, where the LSB corresponds to Bit 0.
6
IAHash
When the received frame’s Destination Address is accepted by the hash filter, this bit is
set if, and only if, RxOK (Bit 8) is set, IAHashA (Register 5, RxCTL, Bit 6) is set, and
Hashed (Bit 9) is set. See Section 5.3.
7
Dribblebits
When set, the received frame has from one to seven bits after the last received full
byte. An "Alignment Error" occurs when Dribblebits and CRCerror (Bit C) are both set.
8
RxOK
When set, the received frame has a good CRC and valid length (i.e., there is not a
CRC error, Runt error, or Extradata error). When RxOK is set, the length of the
received frame is contained at PacketPage base + 0402h. If RxOKiE (Register 3,
RxCFG, Bit 8) is set, there is an interrupt.
9
Hashed
When set, the received frame has a Destination Address that was accepted by the
hash filter. If Hashed
and
RxOK (Bit 8) are set, Bits F-A of RxEvent become the Hash
Table Index for this frame. (See Section 5.3 for an exception regarding broadcast
frames.) If Hashed and RxOK are not
both
set, Bits F-A are individual event bits.
A
IndividualAdr
When the received frame has a Destination Address that matched the Individual
Address found at PacketPage base + 0158h, this bit is set if, and only if, RxOK (Bit 8)
is set
and
IndividualA (Register 5, RxCTL, Bit A) is set.
B
Broadcast
When the received frame has a Broadcast Address (FFFF FFFF FFFFh) as the
Destination Address, this bit is set if, and only if, RxOK is set
and
BroadcastA (Register
5, RxCTL, Bit B) is set.
C
CRCerror
When set, the received frame has a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit
C) is set, there is an interrupt.
D
Runt
When set, the received frame is shorter than 64 bytes. If RuntiE (Register 3, RxCFG,
Bit D) is set, there is an interrupt.
E
Extradata
When set, the received frame is longer than 1518 bytes. All bytes beyond 1518 are
discarded. If ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt.
F
EWAKEevent
Set once when the CS8920A recognizes a received frame as a Magic Packet frame.
Cleared when read. Set again only when another Magic Packet frame is recognized.
This register’s initial state after reset is:
0000 0000
0000 0100
CS8920A
52
DS238PP2
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