參數(shù)資料
型號： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁數(shù)： 72/144頁
文件大?。?/td> 1229K
代理商： CDK8920A
4.6
Initiate Transmit Register
Initiate Transmit Register
Transmit Command Request - TxCMD (Write-only)
F
E
D
TxPadDis InhibitCRC
Address: PacketPage base + 0144h
8
7
Force
TxStart
C
B
A
9
6
5-0
Onecoll
001001
The word written to PacketPage base + 0144h tells the CS8920A how the next packet should be transmitted.
This PacketPage location is write-only, and the written word can be read from Register 9, at PacketPage base +
0108h. The CS8920A does not transmit a frame if TxLength (at PacketPage location base + 0146h) is less than
3. See Section 5.8.
BIT
NAME
DESCRIPTION
5-0
001001
These bits provide an internal address used by the CS8920A to identify this as the
Transmit Command Register. When reading this register, these bits will be 001001,
where the LSB corresponds to Bit 0.
7, 6
TxStart
This pair of bits determines how many bytes are transferred to the CS8920A before the
MAC starts the packet transmit process.
Bit 7 Bit 6
0
0
1
1
0
1
0
1
Start transmission after 5 bytes are in the CS8920A
Start transmission after 381 bytes are in the CS8920A
Start transmission after 1021 bytes are in the CS8920A
Start transmission after the entire frame is in the CS8920A
8
Force
When set in conjunction with a new transmit command, any transmit frames waiting in
the transmit buffer are deleted. If a previous packet has started transmission, that
packet is terminated within 64 bit times with a bad CRC.
9
Onecoll
When this bit is set, any transmission will be terminated after only one collision. When
clear, the CS8920A allows up to 16 normal collisions before terminating the
transmission.
C
InhibitCRC
When set, the CRC is not appended to the transmission.
D
TxPadDis
When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and
InhibitCRC is set, the CS8920A pads to 60 bytes. If the host gives a transmit length
less than 60 bytes and InhibitCRC is clear, then the CS8920A pads to 60 bytes and
appends the CRC.
When TxPadDis is set, the CS8920A allows the transmission of runt frames (a frame
less than 64 bytes). When InhibitCRC is clear, the CS8920A appends the CRC. When
InhibitCRC is set, the CS8920A does not append the CRC.
Because this register is write-only, it’s initial state after reset is undefined.
CS8920A
72
DS238PP2
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