參數(shù)資料
型號(hào)： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁(yè)數(shù)： 16/144頁(yè)
文件大?。?/td> 1229K
代理商： CDK8920A
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eleven of the ISA bus Interrupt Request signals.
Only one interrupt output is used at a time. The
interrupt output is selected during initialization
by writing the interrupt number (0 to 10) into
PacketPage Memory base + 0370h; or, the inter-
rupt output can be accessed through the Plug and
Play resource register 0070h. Unused interrupt
request pins are placed in a high-impedance
state. The selected interrupt request pin goes
high when an enabled interrupt is triggered. The
pin goes low after the Interrupt Status Queue
(ISQ) is read as all 0’s (see Section 5.1 for a
description of the ISQ).
Table 3.1 presents one possible way of connect-
ing the interrupt request pins to the ISA bus that
utilizes commonly available interrupts and facili-
tates board layout.
*When in PnP mode, the interrupt request output
is accessed through the resource register 0370h.
DMA Signals
The CS8920A interfaces directly to the host
DMA controller to provide DMA transfers of re-
ceive frames from CS8920A memory to host
memory. The CS8920A has three pairs of DMA
pins that can be connected directly to the three
16-bit DMA channels of the ISA bus. Only one
DMA channel is used at a time. It is selected
during initialization by writing the number of the
desired channel (0, 1 or 2) into PacketPage
Memory base + 0374h. Unused DMA pins are
placed in a high-impedance state. The selected
DMA request pin goes high when the CS8920A
has received frames to transfer to the host mem-
ory via DMA. If the DMABurst bit (register 17,
BusCTL, Bit B) is set, the pin goes low after the
DMA operation is complete. If the DMABurst
bit is clear, the pin goes low 32
μ
s after the start
of a DMA transfer.
The DMA pin pairs are arranged on the
CS8920A to facilitate board layout. Crystal rec-
ommends the configuration in Table 3.2 when
connecting these pins to the ISA bus.
For a description of DMA mode, see Section
5.5.
3.3
Reset and Initialization
3.3.1
Reset
Nine different conditions cause the CS8920A to
reset its internal registers and circuits.
External Reset, or ISA Reset:
There is a chip-
wide reset whenever the RESET pin is high for
at least 40 ns. During a chip-wide reset, all cir-
cuitry and registers in the CS8920A are reset.
Power-Up Reset:
When power is applied, the
CS8920A maintains reset until the voltage at the
supply pins reaches approximately 2.5 V. The
CS8920A comes out of reset once Vcc is greater
CS8920A Interrupt
Request Pin
IRQ3(Pin 75)
IRQ4 (Pin 76)
IRQ5 (Pin 77)
IRQ6(Pin 78)
IRQ7(Pin 79)
IRQ9(Pin 106)
IRQ10(Pin 34)
IRQ11(Pin 33)
IRQ12(Pin 32)
IRQ14(Pin 30)
IRQ15 (Pin 31)
ISA Bus
Interrupt
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
PacketPage
base + 0370h*
0003h
0004h
0005h
0006h
0007h
0009h
000Ah
000Bh
000Ch
000Eh
000Fh
Table 3.1. Interrupt Assignments
CS8920A DMA
Signal (Pin #)
DRQ5 (16)
DACK5 (17)
DRQ6 (14)
DACK6 (15)
DRQ7 (9)
DACK7 (10)
ISA DMA
Signal
DRQ5
DACK5
DRQ6
DACK6
DRQ7
DACK7
PacketPage
base + 0374h
0000h
0001h
0002h
Table 3.2. DMA Assignments
CS8920A
16
DS238PP2
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