參數(shù)資料
型號： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁數(shù)： 106/144頁
文件大?。?/td> 1229K
代理商： CDK8920A
5.7
StreamTransfer
Overview
The CS8920A supports an optional feature,
StreamTransfer, that can reduce the amount of
CPU overhead associated with frame reception.
StreamTransfer works during periods of high re-
ceive activity by grouping multiple receive
events into a single interrupt, thereby reducing
the number of receive interrupts to the host proc-
essor. During periods of peak loading,
StreamTransfer will eliminate 7 out of every 8
interrupts, cutting interrupt overhead by up to
87%.
Configuring the CS8920A for StreamTransfer
StreamTransfer is enabled by setting the StreamE
bit along with either the AutoRxDMAE bit or the
RxDMAonly bit in register Receiver Configura-
tion (register 3). (StreamTransfer must not be
selected unless either one of AutoRxDMAE or
RxDMA-only is selected.) StreamTransfer only
applies to "good" frames (frames of legal length
with valid CRC). Therefore, the RxOKA bit and
the RxOKiE bit must both be set. Finally,
StreamTransfer works on whole packets and is
not compatible with early interrupts. This re-
quires that the RxDestiE bit and the Rx128iE bit
both be clear.
Table 5.10 summarizes how to configure the
CS8920A for StreamTransfer.
StreamTransfer Operation
When StreamTransfer is enabled, the CS8920A
will initiate a StreamTransfer cycle whenever
two or more frames with the following charac-
teristics are received:
1. have passed the Destination Address filter;
2. are of legal length with valid CRC; and,
3. are spaced "back-to-back" (between 9.6 and 52
μ
s apart).
During a StreamTransfer cycle the CS8920A
does the following:
delays the normal RxOK interrupt associated
with the first receive frame;
switches to receive DMA mode;
transfers up to eight receive frames into host
memory via DMA;
updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register
(PacketPage base + 0028h);
updates DMA Byte Count register (Packet-
Page base + 002Ah);
sets the RxDMAFrame bit (Register C,
BufEvent, Bit 7); and,
generates an RxDMAFrame interrupt.
Keeping StreamTransfer Mode Active
When the CS8920A initiates a StreamTransfer
cycle, it will continue to execute cycles as long
as the following conditions hold true:
Register Name
Register 3, RxCFG
Bit
7
8
9
or
A
8
7
F
B
Bit Name
StreamE
RxOKiE
RxDMAonly
or
AutoRxDMA
RxOKA
RxDMAiE
RxDestiE
Rx128iE
Value
1
1
1
or
1
1
1
0
0
Register 5, RxCTL
Register B, BufCFG
Table 5.10. Stream Transfer Configuration
CS8920A
106
DS238PP2
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