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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 33/144頁 |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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SQE Test:
If the CS8920A is transmitting on the
AUI, the external transceiver should generate an
SQE Test signal on the CI+/CI- pair following
each transmission. The SQE Test is a 10 MHz
signal lasting 5 to 15 bit times and starting
within 0.6 to 1.6
μ
s after the end of transmis-
sion. During this period, the CS8920A ignores
receive carrier activity (see SQE Error in this
section for more information).
3.11
Encoder/Decoder (ENDEC)
The CS8920A’s integrated encoder/decoder (EN-
DEC) circuit is compliant with the relevant
portions of section 7 of the Ethernet standard
(ISO/IEC 8802-3, 1993). Its primary functions
include:
Manchester encoding of transmit data;
informing the MAC when valid receive data is
present (Carrier Detection); and, recovering the
clock and NRZ data from incoming Manchester-
encoded data.
Figure 3.9 provides a block diagram of the EN-
DEC and how it interfaces to the MAC, AUI and
10BASE-T transceiver.
Encoder
The encoder converts NRZ data from the MAC
and a 20 MHz Transmit Clock signal into a se-
rial stream of Manchester data. The Transmit
Clock is produced by an on-chip oscillator cir-
cuit that is driven by either an external 20 MHz
quartz crystal or a TTL-level CMOS clock input.
If a CMOS input is used, the clock should be 20
MHz
±
0.01% with a duty cycle between 40%
and 60%. The specifications for the crystal are
described in section 13.0 (Quartz Crystal Re-
quirements). The encoded signal is routed to
either the 10BASE-T transceiver or AUI, de-
pending on configuration.
Carrier Detection
The internal Carrier Detection circuit informs the
MAC that valid receive data is present by assert-
ing the internal Carrier Sense signal as soon it
detects a valid bit pattern (1010b or 0101b for
10BASE-T, and 1b or 0b for AUI). During nor-
mal packet reception, Carrier Sense remains
asserted while the frame is being received, and is
de-asserted 1.3 to 2.3 bit times after the last low-
to-high transition of the End-of-Frame (EOF)
sequence. Whenever the receiver is idle (no re-
ceive activity), Carrier Sense is de-asserted. The
CRS bit (Register 14, LineST, Bit E) reports the
state of the Carrier Sense signal.
Clock and Data Recovery
When the receiver is idle, the phase-lock loop
(PLL) is locked to the internal clock signal. The
assertion of the Carrier Sense signal interrupts
the PLL. When it restarts, it locks on the incom-
ing data. The receive clock is then compared to
the incoming data at the bit cell center and any
phase difference is corrected. The PLL remains
locked as long as the receiver input signal is
valid. Once the PLL has locked on the incoming
data, the ENDEC converts the Manchester data
to NRZ and passes the decoded data and the re-
covered clock to the MAC for further processing.
Interface Selection
Physical interface selection is determined by the
AUIonly bit (Bit 8) and the AutoAUI/10BT bit
(Bit 9) in the LineCTL register (Register 13).
Table 3.11 describes the possible configurations.
AUIonly
(Bit 8)
0
1
0
AutoAUI/10BT
(Bit 9)
0
N/A
1
Physical
Interface
10BASE-T Only
AUI Only
Auto-Select
Table 3.11. Interface Selection
CS8920A
DS238PP2
33
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