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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 100/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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When the host processes DMAed frames, it must
read the DMA Frame Count register.
Whenever a receive frame is missed (lost) due to
insufficient receive buffer space, the RxMISS
counter (Register 10) is incremented. A missed
receive frame causes the counter to increment in
either DMA or non-DMA modes.
Note that when in DMA mode, reading the con-
tents of the RxEvent register will return 0000h.
Status information should be obtained from the
DMA buffer.
5.5.5
Frame
Committing Buffer Space to a DMAed
Although a receive frame may occupy space in
the host memory’s circular DMA buffer, the
CS8920A’s Memory Manager does not commit
the buffer space to the receive frame until the en-
tire frame has been transferred
and
the host
learns of the frame’s existence by reading the
Frame Count register (PacketPage base + 0028h).
When the CS8920A commits DMA buffer space
to a particular DMAed receive frame (termed a
committed received frame), no data from sub-
sequent frames can be written to that buffer
space until the committed received frame is freed
from commitment. (The committed received
frame may or may not have been received error
free.)
A committed DMAed receive frame is freed
from commitment by any one of the following
conditions:
1. The host re-reads the DMA Frame Count regis-
ter (PacketPage base + 0028h).
2. New frames have been transferred via DMA,
and the host reads the BufEvent register
(either directly or from the ISQ) and sees that
the RxDMAFrame bit is set (Register C, bit
7) (this condition is termed an "implied
Skip").
3. The host issues a Reset-DMA command by
setting the ResetRxDMA bit (Register 17,
BusCTL, Bit 6).
5.5.6
DMA Buffer Organization
When DMA is used to transfer receive frames,
the DMA Start-of-Frame register (PacketPage
Base + 0026h) defines the offset from the DMA
base to the start of the most recently transferred
received frame. Frames stored in the DMA buff-
er are transferred as words and maintain
double-word (32-bit) alignment. Unfilled mem-
ory space between successive frames stored in
the DMA buffer may result from double-word
Non-StreamTransfer Mode
The RxDMAFrame bit is set whenever the DMA
Frame Count register (PacketPage base +
0028h) transitions to non-zero.
StreamTransfer Mode (see Section 5.7)
The RxDMAFrame bit is set at the end of a
StreamTransfer cycle.
To Set RxDMAFrame
To Clear RxDMAFrame The DMA Frame Count is zero.
The DMA Frame Count is zero.
Table 5.9. RxDMAFrame Bit
CS8920A
100
DS238PP2
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