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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 84/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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Command is written. This port is mapped into
PacketPage base + 0146h.
Interrupt Status Queue Port
This port contains the current value of the Inter-
rupt Status Queue (ISQ). The ISQ is located at
PacketPage base + 0120h. For a more detailed
description of the ISQ, see Section 5.1.
PacketPage Pointer Port
The PacketPage Pointer Port is written whenever
the host wishes to access any of the CS8920A’s
internal registers. The first 12 bits (bits 0 through
B) provide the internal address of the target reg-
ister to be accessed during the current operation.
The next three bits (C, D, and E) must be 0. The
last bit (Bit F) indicates whether or not the Pack-
etPage Pointer should be auto-incremented to the
next word location. Figure 4.4 shows the struc-
ture of the PacketPage Pointer.
PacketPage Data Ports 0 and 1
The PacketPage Data Ports are used to transfer
data to and from any of the CS8920A’s internal
registers. Port 0 is used for 16-bit operations and
Ports 0 and 1 are used for 32-bit operations
(lower-order word in Port 0).
I/O Mode Operation
For an I/O Read or Write operation, the AEN pin
must be low, and the 16-bit I/O address on the
ISA System Address bus (SA0 - SA15) must
match the address space of the CS8920A. For a
Read, the IOR pin must be low, and for a Write,
the IOW pin must be low.
Note that the ISA Latchable Address Bus (LA17
- LA23) is not needed for applications that use
only I/O Mode and Receive DMA operation.
Basic I/O Mode Transmit
I/O Mode transmit operations occur in the fol-
lowing order (using interrupts):
1.The host bids for storage of the frame by writ-
ing the Transmit Command to the TxCMD
Port (I/O base + 0004h) and the transmit frame
length to the TxLength Port (I/O base +
0006h).
2.The host reads the BusST register (Register 18)
to see if the Rdy4TxNOW bit (Bit 8) is set. To
read the BusST register, the host must first set
the PacketPage Pointer at the correct location
by writing 0138h to the PacketPage Pointer
Port (I/O base + 000Ah). It can then read the
BusST register from the PacketPage Data Port
(I/O base + 000Ch). When Rdy4TxNOW is
set, the frame can be written. When clear, the
host must wait for CS8920A buffer memory to
become available. When Rdy4TxiE (Register
B, BufCFG, Bit 8) is set, the host will be in-
terrupted when Rdy4Tx (Register C, BufEvent,
Bit 8) becomes set. When the TxBidErr bit
(Register 18, BusST, Bit 7) is set, the transmit
length is not valid.
3.When the CS8920A is ready to accept the
frame, the host executes repetitive write in-
structions (REP OUT) to the Receive/Transmit
Data Port (I/O base + 0000h) to transfer the
1
0
3
2
5
4
7
6
PacketPage Register Address
9
8
B A
D C
F
E
I/O base + 000Bh
I/O base + 000Ah
Bit F: 0 = Pointer remains fixed
1 = Auto-Increments to next word location
Figure 4.4. PackagePage Pointer
0
1
1
CS8920A
84
DS238PP2
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