參數(shù)資料
型號： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁數(shù)： 66/144頁
文件大小： 1229K
代理商： CDK8920A
Register 17: Bus Control (BusCTL, Read/Write)
Address: PacketPage base + 0116h
F
E
D
C
B
A
9
8
7
6
5-0
EnableIRQ
RxDMA
size
IOCH
RDYE
DMABurst
MemoryE
UseSA
Reset
RxDMA
010111
BusCTL controls the operation of the ISA-bus interface.
BIT
NAME
DESCRIPTION
5-0
010111
These bits provide an internal address used by the CS8920A to identify this as the Bus
Control Register.
6
ResetRxDMA
When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero.
When the host sets this bit, the CS8920A does the following:
1. Terminates the current receive DMA activity, if any.
2. Clears all internal receive buffers.
3. Zeroes the RxDMA offset pointer.
The CS8920A acts upon this command only once when this bit is set. ResetRxDMA is
an Act-Once bit. To cause the pointer to reset again, the host must rewrite a 1.
9
UseSA
When set, the MCS16 pin goes low whenever the address on the SA bus [13..16] and
LA[17:23] match the CS8920A’s assigned Memory base address. When clear, MCS16
is driven low whenever LA[17:23] match the CS8920A’s assigned memory base
address. MCS16 is driven by the CS8920A in Memory Mode with the MemoryE bit
(Register 17, BusCTL, Bit A) set.
A
MemoryE
When set, the CS8920A may operate in Memory Mode. When clear, Memory Mode is
disabled. I/O Mode is always enabled.
B
DMABurst
When clear, the CS8920A performs continuous DMA until the receive frame is
completely transferred from the CS8920A to host memory. When set, each DMA
access is limited to 28
μ
s, after which time the CS8920A gives up the bus for 1.3
μ
s
before making a new DMA request.
C
IOCHRDYE
When set, the CS8920A does not use the IOCHRDY output pin, and the pin is always
in the high-impedance state. This allows external pull-up to force the output high. When
clear, the CS8920A drives IOCHRDY low to request additional time during I/O Read
and Memory Read cycles. IOCHRDY does not affect I/O Write, Memory Write, nor DMA
Read.
D
RxDMAsize
This bit determines the size of the receive DMA buffer (located in host memory).
When set, the DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes.
F
EnableIRQ
When set, the CS8920A will generate an interrupt in response to an interrupt event
(Section 5.1). When cleared, the CS8920A will not generate any interrupts.
After reset, if no EEPROM is found by the CS8920A, the register has the following initial state. If an EEPROM is
found, the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000
0001 0111
CS8920A
66
DS238PP2
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