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| 型號(hào)： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 57/144頁(yè) |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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Register B: Buffer Configuration (BufCFG, Read/Write)
Address: PacketPage base + 010Ah
F
E
D
C
B
A
9
8
7
6
5-0
RxDestiE
Miss
OvfloiE
TxCol
OvfloiE
Rx128iE
RxMissiE
TxUnder
runiE
Rdy4TxiE
RxDMAiE
SWint-X
001011
Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there
is no interrupt.
BIT
NAME
DESCRIPTION
5-0
001011
These bits provide an internal address used by the CS8920A to identify this as the
Buffer Configuration Register.
6
SWint-X
When set, there is an interrupt requested by the host software. The CS8920A provides
the interrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8920A acts
upon this command at once. SWint-X is an Act-Once bit. To generate another interrupt,
rewrite a 1 to this bit.
7
RxDMAiE
When set, there is an interrupt when a frame has been received andDMA is complete.
With this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set.
8
Rdy4TxiE
When set, there is an interrupt when the CS8920A is ready to accept a frame from the
host for transmission. (See Section 5.8 for a description of the transmit bid process.)
9
TxUnderruniE
When set, there is an interrupt if the CS8920A runs out of data before it reaches the
end of the frame (called a transmit underrun). When this happens, event bit
TXUnderrun (Register C, BufEvent, Bit 9) is set and the CS8920A makes no further
attempts to transmit that frame. If the host still wants to transmit that particular frame,
the host must go through the transmit request process again.
A
RxMissiE
When set, there is an interrupt if one or more received frames are lost due to slow
movement of receive data out of the receive buffer (called a receive miss). When this
happens, the RxMiss bit (Register C, BufEvent, Bit A) is set.
B
Rx128iE
When set, there is an interrupt after the first 128 bytes of a frame have been received.
This allows a host processor to examine the Destination Address, Source Address,
Length, Sequence Number, and other information before the entire frame is received.
This interrupt should not be used with DMA. If either AutoRxDMA (Register 3, RxCFG,
Bit A) or RxDMAonly (Register 3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear.
Do not set this bit when StreamTransfer mode is enabled.
C
TxColOvfiE
When set, there is an interrupt when the TxCOL counter increments from 1FFh to
200h. (The TxCOL counter (Register 12) is incremented whenever the CS8920A sees
that the RXD+/RXD- pins (10BASE-T) or the CI+/CI- pins (AUI) go active while a
packet is being transmitted.)
Continued on the next page.
CS8920A
DS238PP2
57
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