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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 113/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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memory to CS8920A memory using “REP” in-
struction (REP MOVS to memory base + 0A00h
in memory mode, and REP OUT to Re-
ceive/Transmit Data Port (I/O base + 0000h) in
I/O mode).
5.8.7
Transmit in Interrupt Mode
In interrupt mode, Rdy4TxiE bit (Register B
“BufCFG”, Bit 8) must be set for transmit opera-
tion. Transmit operation occurs in the following
order and is shown in Figure 5.13
1. The host bids for frame storage by writing the
Transmit Command to the TxCMD register
(memory base + 0144h in memory mode or
I/O base + 0004h in I/O mode).
2. The host writes the transmit frame length to the
TxLength register (memory base + 0146h in
memory mode or I/O base + 0006h in I/O
mode). If the transmit length is erroneous, the
command is discarded and the TxBidErr, bit
7, in BusST (Register 18) is set.
3. The host reads the BusST register. This read is
performed in memory mode by reading Regis-
ter 18, at memory base + 0138h. In I/O mode,
the host must first set the PacketPage Pointer
at the correct location by writing 0138h to the
PacketPage Pointer Port (I/O base + 000Ah),
it than can read the BusST register from the
PacketPage Data Port (I/O base + 000Ch).
After reading the register, the Rdy4TxNOW
bit is checked. If the bit is set, the frame can
be written to CS8920A memory. If
Rdy4TxNOW is clear, the host will have to
wait for the CS8920A buffer memory to be-
come available at which time the host will be
interrupted. On interrupt, the host enters the
interrupt service routine and reads ISQ regis-
ter (Memory base + 0120h in memory mode
or I/O base + 0008h in I/O) and checks the
Rdy4Tx bit (bit 8). If Rdy4Tx is clear then
the CS8920A waits for the next interrupt. If
Rdy4Tx is set, then the CS8920A is ready to
accept the frame.
4. When the CS8920A is ready to accept the
frame, the host transfers the entire frame from
host memory to CS8920A memory using
“REP” instruction (REP MOVS to memory
base + 0A00h in memory mode, and REP
OUT to Receive/Transmit Data Port (I/O base
+ 0000h) in I/O mode).
5.8.8
Completing Transmission
When the CS8920A successfully completes
transmitting a frame, it sets the TxOK bit (Regis-
ter 8, TxEvent, Bit 8). If the TxOKiE bit
(Register 7, TxCFG, bit 8) is set, the CS8920A
generates a corresponding interrupt.
5.8.9
Rdy4TxNOW vs. Rdy4Tx
The Rdy4TxNOW bit (Register 18, BusST, bit 8)
is used to tell the host that the CS8920A is ready
to accept a frame for transmission. This bit is
used during the Transmit Request process or af-
ter the Transmit Request process to signal the
host that space has become available when inter-
rupts are not being used (i.e. the Rdy4TxiE bit
(Register B, BufCFG, Bit 8) is not set). Also, the
Rdy4Tx bit is used with interrupts and requires
the Rdy4TxiE bit be set.
Figures 5.12 & 5.13 provide diagrams of error
free transmission without collision.
For Revision B of CS8920A, if DMA mode is
used for receive operation, Rdy4Tx interrupt may
not occur every time. After servicing a RxDMA
interrupt, check the bit Rdy4TxNow to take ap-
propriate action.
5.8.10
Transmit Frame
Committing Buffer Space to a
When the host issues a transmit request, the
CS8920A checks the length of the transmit
CS8920A
DS238PP2
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