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參數(shù)資料
| 型號(hào)： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 94/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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The BufferCRC bit (Register 3, RxCFG, Bit
B) is set causing the 4-byte CRC to be buff-
ered with the rest of the receive data.
The RxOKA bit (Register 5, RxCTL, Bit 8)
is set, causing the CS8920A to accept good
frames (a good frame is one with legal length
and valid CRC).
The RxOKiE bit (Register 3, RxCFG, Bit 8)
is set, causing an interrupt to be generated
whenever a good frame is received.
Then the transfer to the host would proceed as
follows:
1. The CS8920A generates an RxOK interrupt to
the host to signal the arrival of a good frame.
2. The host reads the ISQ (PacketPage base +
0120h) to assess the status of the receive
frame and sees the contents of the RxEvent
register (Register 4) with the RxOK bit (Bit 8)
set.
3. The host reads the receive frame’s length from
the RxLength register (PacketPage base +
0402h).
4. The host reads the frame data by executing 32
consecutive MOV instructions from Packet-
Page base + 0404h.
The memory map of the 64-byte frame is given
in Table 5.5.
5.2.9
Receive Frame Byte Counter
The receive frame byte counter describes the
number of bytes received for the current frame.
The counter is incremented in real time as bytes
are received from the Ethernet. The byte counter
can be used by the driver to determine how many
bytes are available for reading out of the
CS8920A. Maximum Ethernet throughput can be
achieved by using I/O or memory modes, and by
dedicating the CPU to reading this counter, and
using the count to read the frame out of the
CS8920A at the same time it is being received
by the CS8920A from the Ethernet (parallel
frame-reception and frame-read-out tasks).
The byte count register resides at PacketPage
base + 50h.
Following an RxDest or Rx128 interrupt, the
register contains the number of bytes which are
available to be read by the CPU. When the end
of frame is reached, the count contains the final
count value for the frame, including the allow-
ance for the BufferCRC option. When this final
count is read by the CPU, the count register is
set to zero. Therefore, to read a complete frame
using the byte count register, the register can be
read and the data moved until a count of zero is
detected. The RxEvent register can then be read
to determine the final frame status.
The sequence is as follows:
1. At the start of a frame, the byte counter
matches the incoming character counter.
2. At the end of the frame, the final count includ-
ing the allowance for the CRC (if the
Memory Space
Word Offset
0400h
Description of Data Stored in On-
chip RAM
RxStatus Register (the host may
skip reading 0400h since
RxEvent was read from the ISQ.)
RxLength Register (In this
example, the length is 40h bytes.
The frame starts at 0404h, and
runs through 0443h.)
6-byte Destination Address.
6-byte Source Address.
2-byte Length or Type Field.
46 bytes of data.
CRC, bytes 1 and 2
CRC, bytes 3 and 4
0402h
0404h to 0409h
040Ah to 040Fh
0410h to 011h
0412h to 043Fh
0440h
0442h
Table 5.5. Example Memory Map
CS8920A
94
DS238PP2
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