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參數(shù)資料
| 型號(hào)： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 80/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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4.9
Locations
Receive and Transmit Frame
The Receive and Transmit Frame PacketPage lo-
cations are used to transfer Ethernet frames to
and from the host. The host sequentially writes
to and reads from these locations, and internal
buffer memory is dynamically allocated between
transmit and receive as needed. One receive
frame and one transmit frame are accessible at a
time.
Receive PacketPage Locations
In I/O mode, the receive status/length/frame lo-
cations are read through repetitive reads from
one I/O port at the I/O base address. See Section
4.12.
In memory mode, the receive status/length/frame
locations are read using memory reads of a block
of memory starting at memory base address +
0400h. Typically the memory locations are read
sequentially using repetitive Move instructions
(REP MOVS). See Table 4.4 and Section 4.11.
The first 118 bytes of the receive frame can be
accessed randomly if word reads on even word
boundaries are used. Beyond 118 bytes, the
memory reads must be sequential. Byte reads, or
reads on odd-word boundaries, can be performed
only in sequential read mode. See Section 4.10.
The RxStatus word reports the status of the cur-
rent received frame. RxEvent register 4
(PacketPage base + 0124h) has the same contents
as the RxStatus register, except RxEvent is
cleared when RxEvent is read. See Section 5.2.
The RxLength (receive length) word is the
length, in bytes, of the data to be transferred to
the host across the ISA bus. The register de-
scribes the length from the start of Source
Address to the end of CRC, assuming that CRC
has been selected (via Register 3 RxCFG, bit
BufferCRC). If CRC has not been selected, then
the length does not include the CRC, and the
CRC is not present in the receive buffer.
After the RxLength has been read, the receive
frame can be read. Once some portion of the
frame is read, the entire frame should be read
before reading the RxEvent register either di-
rectly or through the ISQ register. Reading the
RxEvent register signals to the CS8920A that the
host is finished with the current frame and wants
to start processing the next frame. In this case,
the current frame will no longer be accessible to
the host. The current frame will also become in-
accessible if a Skip command is issued, or if the
entire frame has been read. See Section 5.2.
Transmit Locations
The host can write frames into the CS8920A
buffer using Memory writes using REP MOVS
to the TxFrame location. See Section 5.8.
4.10
Eight and Sixteen Bit Transfers
A data transfer to or from the CS8920A can be
done in either I/O or Memory space, and can be
either 16 bits wide (word transfers) or 8 bits
wide (byte transfers). Because the CS8920A’s in-
ternal architecture is based on a 16-bit data bus,
word transfers are the most efficient.
Description Mnemonic Read/Write
Location:
PacketPage base +
0400h-0401h
Receive
Status
Receive
Length
Receive
Frame
Transmit
Frame
RxStatus
Read-only
RxLength
Read-only
0402h-0403h
RxFrame
Read-only
starts at 0404h
TxFrame
Write-only
starts at 0A00h
Table 4.4. Receive/Transmit Memory
Locations
CS8920A
80
DS238PP2
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