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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 46/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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Three 10-bit counters are included with the
Status and Event registers. RxMISS counts
missed receive frames, TxCOL counts transmit
collisions, and TDR is a time domain reflectome-
ter useful in locating cable faults. The following
sections contain more information about these
counters.
Table 4.2 provides a summary of PacketPage
Register types.
4.4.1
Status and Control Bit Definitions
This section provides a description of the special
bit types used in the Status and Control registers.
Section 4.4 provides a detailed description of the
bits in each register.
Act-Once Bits
There are four bits that cause the CS8920A to
take a certain action only once when set. These
Act-Once bits are: Skip_1 (Register 3, RxCFG,
Bit 6), RESET (Register 15, SelfCTL, Bit 6),
ResetRxDMA (Register 17, BusCTL, Bit 6), and
SWint-X (Register B, BufCFG, Bit 6). To cause
the action again, the host must set the bit again.
Act-Once bits are always read as clear.
Temporal Bits
Temporal bits are bits that are set and cleared by
the CS8920A without intervention by the host
processor. This includes all status bits in the four
status registers (Register 14, LineST; Register 16,
SelfST; Register 18, BusST; and Register 1E,
AutoNegSt), the RxDest bit (Register C,
BufEvent, Bit F), and the Rx128 bit (Register C,
BufEvent, Bit B). Like all Event bits, RxDest
and Rx128 are cleared when read by the host.
Interrupt Enable Bits and Events
Interrupt Enable bits end with the suffix iE and
are located in three Configuration registers:
RxCFG (Register 3), TxCFG (Register 7), and
BufCFG (Register B). Each Interrupt Enable bit
corresponds to a specific event. If an Interrupt
Enable bit is set and its corresponding event oc-
curs, the CS8920A generates an interrupt to the
host processor.
The bits that report when various events occur
are located in three Event registers and two
Suffix
Type
Description
Comments
CMD
CFG
Read/Write
Read/Write
Command:
Written once per frame to initiate transmit.
Configuration:
Written at setup and used to determine what
frames will be transmitted and received and what events will cause
interrupts.
Control:
Written at setup and used to determine what frames will
be transmitted and received and how the physical interface will be
configured.
Event:
Reports the status of transmitted and received frames.
CTL
Read/Write
Event
Read-only
cleared when
read
ST
Read-only
Status:
Reports information about the configuration of the
CS8920A.
Counters:
Counts missed receive frames and collisions. Provides
time domain reflectometer for locating coax cable faults.
Read-only
cleared when
read
Table 4.2. PacketPage Register Types
CS8920A
46
DS238PP2
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