參數(shù)資料
型號(hào)： CDK8920A
廠商： Cirrus Logic, Inc.
英文描述： CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER
中文描述： 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器
文件頁(yè)數(shù)： 15/144頁(yè)
文件大?。?/td> 1229K
代理商： CDK8920A
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tion, the CS8920A provides the capability to
switch between Memory or I/O operation and
DMA operation by using Auto-Switch DMA and
StreamTransfer.
Sections 5.2 through 5.7 provide a detailed de-
scription of packet reception.
Reset/Boot/Sleep
Nine resets can be activated on the CS8920A.
Three are activated by the V
CC
power supply
line; one is activated when the EEPROM fails
checksum; one is activated on a Plug and Play
instruction; one is activated when RESET is set;
and three are activated with sleep modes.
A sleep mode disables the CS8920A (completely
or partially) to reduce power consumption. "Sus-
pend" describes the CS8920A in the completely
disabled mode. "Standby" describes the
CS8920A in the partially disabled mode when
most of its circuits except the receiver are dis-
abled. The CS8920A can be "Awakened" when
the receiver detects and receives line activity.
After reset, packet transmission and reception are
disabled. Either an external EEPROM must be
used to start the CS8920A, or the host must di-
rectly set up registers using Plug and Play
protocols.
Contact Crystal’s CS8920A technical support for
more information regarding the use of the
CS8920A without an external EEPROM.
3.2
ISA Bus Interface
The CS8920A provides a direct interface to ISA
buses running at clock rates from 8 to 11 MHz.
Its on-chip bus drivers are capable of delivering
24 mA of drive current, allowing the CS8920A
to drive the ISA bus directly, without added ex-
ternal "glue logic".
The CS8920A is optimized for 16-bit data trans-
fers, operating in either Memory space, I/O
space, or as a DMA slave.
Note that ISA-bus operation below 8 MHz
should use the CS8920A’s Receive DMA mode
to minimize missed frames. See Section 5.5 for a
description of Receive DMA operation.
Memory Mode Operation
When configured for Memory Mode operation,
the CS8920A’s internal RAM is mapped into a
contiguous 4-Kbyte block of host memory, pro-
viding the host with direct access to the
CS8920A’s internal registers and frame buffers.
The host initiates Read operations by driving the
MEMR pin low and Write operations by driving
the MEMW pin low.
For additional information about Memory Mode,
see Section 4.11.
I/O Mode Operation
When configured for I/O Mode operation, the
CS8920A is accessed through eight, 16-bit I/O
ports that are mapped into sixteen contiguous
I/O locations in the host system’s I/O space. I/O
Mode is the default configuration for the
CS8920A and is always enabled.
For an I/O Read or Write operation, the AEN pin
must be low, and the 16-bit I/O address on the
ISA System Address bus (SA0 - SA15) must
match the address space of the CS8920A. For a
Read, IOR must be low, and for a Write, IOW
must be low.
For additional information about I/O Mode, see
Section 4.12.
Interrupt Request Signals
The CS8920A has eleven interrupt request out-
put pins that can be connected directly to any
CS8920A
DS238PP2
15
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