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參數(shù)資料
| 型號(hào)： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 90/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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Choosing How to Transfer Frames:
The RxCFG
register (Register 3) and the BusCTL register
(Register 17) are used to determine how frames
will be transferred to host memory, as described
in Table 5.4.
5.2.3
Receive Frame Pre-Processing
The CS8920A pre-processes all receive frames
using a four step process:
1. Destination Address filtering;
2. Early Interrupt Generation;
3. Acceptance filtering; and,
4. Normal Interrupt Generation.
Figure 5.3 provides a diagram of frame pre-
processing.
Destination Address Filtering:
All incoming
frames are passed through the Destination Ad-
dress filter (DA filter). If the frame’s DA passes
the DA filter, the frame is passed on for further
pre-processing. If it fails the DA filter, the frame
is discarded. See Section 5.3 for a more detailed
description of DA filtering.
Early Interrupt Generation:
The CS8920A sup-
ports the following two early interrupts that can
be used to inform the host that a frame is being
received:
RxDest: The RxDest bit (Register C,
BufEvent, Bit F) is set as soon as the Desti-
nation Address (DA) of the incoming frame
passes the DA filter. When the RxDestiE bit
(Register B, BufCFG, bit F) is set, the
CS8920A generates a corresponding inter-
rupt. When RxDest is set, the host is
allowed to read the incoming frame’s DA
(the first 6 bytes of the frame).
Rx128: The Rx128 bit (Register C,
BufEvent, Bit B) is set as soon as the first
128 bytes of the incoming frame have been
received. When the Rx128iE bit (Register B,
BufCFG, bit B) is set, the CS8920A gener-
ates a corresponding interrupt. When the
Rx128 bit is set, the RxDest bit is cleared
and the host is allowed to read the first 128
bytes of the incoming frame. The Rx128 bit
is cleared by the host reading the BufEvent
register (either directly or through the Inter-
rupt Status Queue) or by the CS8920A
Register B, BufCFG
Bit
7
Bit Name
RxDMAiE
Operation
When set, there is an interrupt if one or
more frames are transferred via DMA.
When set, there is an interrupt if a
frame is missed due to insufficient
receive buffer space.
When set, there is an interrupt after the
first 128 bytes of receive data have
been buffered.
RxMISS counter overflows.
RxDestiE
When set, there is an interrupt after the
DA of an incoming frame has been
buffered.
A
RxMissiE
B
Rx128iE
D
F
Table 5.3. Registers 3 & B
Interrupt Configuration
Register 3, RxCFG
Bit
7
9
Bit Name
StreamE
RxDMAonly When set, DMA slave operation used
for all receive frames.
AutoRx
DMAE
Register 17, BusCTL
Bit Name
DMABurst
When set, DMA operations hold the
bus for up to approximately 28
μ
s.
When clear, DMA operations are
continuous.
RxDMAsize When set, DMA buffer size is 64
Kbytes. When clear, DMA buffer size is
16 Kbytes.
Operation
When set, StreamTransfer enabled.
A
When set, Auto-Switch DMA enabled.
Bit
B
Operation
F
Table 5.4. Frame Transfer Method
CS8920A
90
DS238PP2
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