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參數資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍的ISA即插即用，即插即用以太網控制器 |
| 文件頁數： | 36/144頁 |
| 文件大小： | 1229K |
| 代理商： | CDK8920A |
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Prior to enabling Auto-Negotiation, the Al-
lowFDX bit (Register 1D, AutoNegCTL, Bit 7)
should be set if full-duplex operation is to be al-
lowed and reset otherwise. If this bit is reset,
only half-duplex operation will be negotiated.
To enable Auto-Negotiation the host should set
the AutoNegEnable bit (Register 1D,
AutoNegCTL, Bit 8) and reset the NLPEnable
bit (Register 1D, AutoNegCTL, Bit 9) and the
ForceFDX bit (Register 1D, AutoNegCTL, Bit
F).
Re-negotiation can be forced to occur by setting
the ReNOW bit (Register 1D, AutoNegCTL, bit
6). Typically, this is done after a change in the
settings of the Auto-Negotiation bits, in order to
cause the new settings to be acted upon.
The NLPEnable bit (Register 1D, AutoNegCTL,
bit 9) overrides the Auto-Negotiation settings
and causes Normal Link Pulses to be transmitted
by the CS8920A. Auto-Negotiation is disabled.
The following section describes the operation of
the CS8920A in NLP mode.
Link Pulse Detection
To prevent disruption of network operation due
to a faulty link segment, the CS8920A continu-
ally monitors the 10BASE-T receive pair
(RXD+/ RXD-) for packets and link pulses. Af-
ter each packet or link pulse is received, an
internal Link-Loss timer is started. As long as a
packet or link pulse is received before the Link-
Loss timer finishes (between 25 and 150 ms),
the CS8920A maintains normal operation. If no
receive activity is detected, the CS8920A dis-
ables packet transmission to prevent "blind"
transmissions onto the network (link pulses are
still sent while packet transmission is disabled).
To reactivate transmission, the receiver must de-
tect a single packet (the packet itself is ignored),
or two link pulses separated by more than 2 to 7
ms and no more than 25 to 150 ms (see section
10.0 for 10BASE-T timing).
The state of the link segment is reported in the
LinkOK bit (Register 14, LineST, Bit 7). If the
HC0E bit (Register 15, SelfCTL, Bit C) is clear,
it is also indicated by the output of the
LINKLED pin. If the link is "good", the LinkOK
bit is set and the LINKLED pin is driven low. If
the link is "bad" the LinkOK bit is clear and the
LINKLED pin is high. To disable this feature,
the host must set the DisableLT bit (Register 19,
TestCTL, Bit 7). If DisableLT is set, the
CS8920A will transmit and receive packets inde-
pendent of the link segment.
Receive Polarity Detection and Correction
The CS8920A automatically checks the polarity
of the receive half of the twisted pair cable. If
the polarity is correct, the PolarityOK bit (Regis-
ter 14, LineST, bit C) is set. If the polarity is
reversed, the PolarityOK bit is clear. If the Polar-
ityDis bit (Register 13, LineCTL, Bit C) is clear,
Packet
less than
16 ms
16 ms
16 ms
Link
Pulse
Link
Pulse
Time
Packet
Figure 3.11. Link Pulse Transmission
CS8920A
36
DS238PP2
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