II CORE BLOCK: CPU AND OPERATING MODE
S1C33T01 FUNCTION PART
EPSON
B-II-2-5
Table 2.1
Trap Table (continue)
HEX
No.
Vector number
(Hex address)
Exception/interrupt name
Exception/interrupt factor
IDMA
Ch.
Priority
3C
60(Base+F0)
Serial interface Ch.1
Receive error
–
High
3D
61(Base+F4)
Receive buffer full
25
↑
3E
62(Base+F8)
Transmit buffer empty
26
63
reserved
–
40
64(Base+100)
A/D converter
A/D converter, end of conversion
27
41
65(Base+104)
Clock timer
Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
1-minuet, 1-hour or specified time count up
–
66–67
reserved
–
44
68(Base+110)
Port input interrupt 4
Edge (rising or falling) or level (High or Low)
28
45
69(Base+114)
Port input interrupt 5
Edge (rising or falling) or level (High or Low)
29
46
70(Base+118)
Port input interrupt 6
Edge (rising or falling) or level (High or Low)
30
47
71(Base+11C)
Port input interrupt 7
Edge (rising or falling) or level (High or Low)
31
48
72(Base+120)
8-bit programmable timer
Timer 4 underflow
32
49
73(Base+124)
Timer 54 underflow
33
74-75
reserved
4C
76(Base+130)
Serial interface Ch.2
Receive error
4D
77(Base+134)
Receive buffer full
34
4E
78(Base+138)
Transmit buffer empty
35
79
reserved
50
80(Base+140)
Serial interface Ch.3
Receive error
51
81(Base+144)
Receive buffer full
36
52
82(Base+148)
Transmit buffer empty
37
83
reserved
54
84(Base+150)
Port input interrupt 8
Edge (rising or falling) or level (High or Low)
38
55
85(Base+154)
Port input interrupt 9
Edge (rising or falling) or level (High or Low)
39
56
86(Base+158)
Port input interrupt 10
Edge (rising or falling) or level (High or Low)
40
57
87(Base+15C)
Port input interrupt 11
Edge (rising or falling) or level (High or Low)
41
58
88(Base+160)
Port input interrupt 12
Edge (rising or falling) or level (High or Low)
42
59
89(Base+164)
Port input interrupt 13
Edge (rising or falling) or level (High or Low)
43
5A
90(Base+168)
Port input interrupt 14
Edge (rising or falling) or level (High or Low)
44
5B
91(Base+16C)
Port input interrupt 15
Edge (rising or falling) or level (High or Low)
45
92-93
reserved
5E
94(Base+178)
16-bit programmable timer 6
Timer 6 comparison B
46
5F
95(Base+17C)
Timer 6 comparison A
47
96-97
reserved
62
98(Base+188)
16-bit programmable timer 7
Timer 7 comparison B
48
63
99(Base+18C)
Timer 7 comparison A
49
100-101
reserved
66
102(Base+198) 16-bit programmable timer 8
Timer 8 comparison B
50
67
103(Base+19C)
Timer 8 comparison A
51
104-105
reserved
6A
106(Base+1A8) 16-bit programmable timer 9
Timer 9 comparison B
52
6B
107(Base+1AC)
Timer 9 comparison A
53
6C
108(Base+1B0) Single-master I2C-bus Ch. 0
Command complete/error occurred
6D
109(Base+1B4)
Read DMA request
54
6E
110(Base+1B8)
Write DMA request
55
111
reserved
70
112(Base+120) Single-master I2C-bus Ch. 1
Command complete/error occurred
71
113(Base+120)
Read DMA request
56
72
114(Base+120)
Write DMA request
57
↓
115
reserved
Low
Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default.