
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33T01 FUNCTION PART
EPSON
B-III-10-19
I/O Memory for Input Interrupts
Table 10.10 shows the control bits for the port input and key input interrupts.
Table 10.10
Control Bits for Input Interrupts
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
–
0 to 7
–
–
PP1L2
PP1L1
PP1L0
–
PP0L2
PP0L1
PP0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 1 interrupt level
reserved
Port input 0 interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
0040260
(B)
Port input 0/1
interrupt
priority register
–
0 to 7
–
–
PP3L2
PP3L1
PP3L0
–
PP2L2
PP2L1
PP2L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Port input 3 interrupt level
reserved
Port input 2 interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
0040261
(B)
Port input 2/3
interrupt
priority register
–
0 to 7
–
–
PK1L2
PK1L1
PK1L0
–
PK0L2
PK0L1
PK0L0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
Key input 1 interrupt level
reserved
Key input 0 interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
0040262
(B)
Key input
interrupt
priority register
–
EK1
EK0
EP3
EP2
EP1
EP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
–
0
–
R/W
0 when being read.
0040270
(B)
1 Enabled
0 Disabled
Key input,
port input 0–3
interrupt
enable register
–
EP7
EP6
EP5
EP4
ECTM
EADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
–
0
–
R/W
0 when being read.
0040277
(B)
1 Enabled
0 Disabled
Port input 4–7,
clock timer,
A/D interrupt
enable register
–
FK1
FK0
FP3
FP2
FP1
FP0
D7–6
D5
D4
D3
D2
D1
D0
reserved
Key input 1
Key input 0
Port input 3
Port input 2
Port input 1
Port input 0
–
X
–
R/W
0 when being read.
0040280
(B)
1 Factor is
generated
0 No factor is
generated
Key input,
port input 0–3
interrupt factor
flag register
–
FP7
FP6
FP5
FP4
FCTM
FADE
D7–6
D5
D4
D3
D2
D1
D0
reserved
Port input 7
Port input 6
Port input 5
Port input 4
Clock timer
A/D converter
–
X
–
R/W
0 when being read.
0040287
(B)
1 Factor is
generated
0 No factor is
generated
Port input 4–7,
clock timer, A/D
interrupt factor
flag register
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
0040290
(B)
1 IDMA
request
0 Interrupt
request
Port input 0–3,
high-speed
DMA, 16-bit
timer 0
IDMA request
register