4
PERIPHERAL CIRCUITS
A-40
EPSON
S1C33T01 PRODUCT PART
Table 4.2.1
I/O Memory Map (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
–
0 to 7
–
–
P12C12
P12C11
P12C10
–
P12C02
P12C01
P12C00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1
interrupt level
reserved
I2CSMST Ch.0
interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
00402B0
(B)
Single-master
I2C-bus Ch.0/1
interrupt
priority
register
–
E12CW1
E12CR1
E12CI1
E12CW0
E12CR0
E12CI0
D7–6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMA request
I2CSMST Ch.1 request
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
I2CSMST Ch.0 request
–
0
–
R/W
0 when being read.
00402B1
(B)
1 Enabled
0 Disabled
Single-master
I2C-bus Ch.0/1
interrupt
ebable
register
–
F12CW1
F12CR1
F12CI1
F12CW0
F12CR0
F12CI0
D7–6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMA request
I2CSMST Ch.1 request
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
I2CSMST Ch.0 request
–
0
–
R/W
0 when being read.
00402B2
(B)
1 Factor is
generated
0 No factor is
generated
Single-master
I2C-bus Ch.0/1
interrupt
factor flag
register
–
R12CW1
R12CR1
R12CW0
R12CR0
D7–4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMArequest
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
–
0
–
R/W
0 when being read.
00402B3
(B)
–
1 IDMA
request
0 Interrupt
request
Single-master
I2C-bus Ch.0/1
IDMA
request
register
–
DE12CW1
DE12CR1
DE12CW0
DE12CR0
D7–4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMArequest
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
–
0
–
R/W
0 when being read.
00402B4
(B)
–
1 IDMA
enabled
0 IDMA
disabled
Single-master
I2C-bus Ch.0/1
IDMA
enable
register
–
CFK54
CFK53
CFK52
CFK51
CFK50
D7–5
D4
D3
D2
D1
D0
reserved
K54 function selection
K53 function selection
K52 function selection
K51 function selection
K50 function selection
–
0
–
R/W
0 when being read.
00402C0
(B)
1 #DMAREQ3 0 K54
1 #DMAREQ2 0 K53
1 #ADTRG
0 K52
1 #DMAREQ1 0 K51
1 #DMAREQ0 0 K50
K5 function
select register
–
K54D
K53D
K52D
K51D
K50D
D7–5
D4
D3
D2
D1
D0
reserved
K54 input port data
K53 input port data
K52 input port data
K51 input port data
K50 input port data
–
R
0 when being read.
00402C1
(B)
1 High
0 Low
K5 input port
data register
CFK67
CFK66
CFK65
CFK64
CFK63
CFK62
CFK61
CFK60
D7
D6
D5
D4
D3
D2
D1
D0
K67 function selection
K66 function selection
K65 function selection
K64 function selection
K63 function selection
K62 function selection
K61 function selection
K60 function selection
0
R/W
00402C3
(B)
1 AD7
0 K67
1 AD6
0 K66
1 AD5
0 K65
1 AD4
0 K64
1 AD3
0 K63
1 AD2
0 K62
1 AD1
0 K61
1 AD0
0 K60
K6 function
select register
K67D
K66D
K65D
K64D
K63D
K62D
K61D
K60D
D7
D6
D5
D4
D3
D2
D1
D0
K67 input port data
K66 input port data
K65 input port data
K64 input port data
K63 input port data
K62 input port data
K61 input port data
K60 input port data
–
R
00402C4
(B)
1 High
0 Low
K6 input port
data register