III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
S1C33T01 FUNCTION PART
EPSON
B-III-10-13
Selecting input pins
The interrupt factors allows selection of an input pin from the four predefined pins independently.
Table 10.5 shows the control bits and the selectable pins for each factor.
Table 10.5
Selecting Pins for Port Input Interrupts
Interrupt
Control bit
SPTEX=0
SPTEX=1
factor
SPT settings
11
10
01
11
FPT15
P57
FPT14
P56
FPT13
P55
FPT12
P54
FPT11
P53
FPT10
P52
FPT9
P51
FPT8
P50
FPT7
SPT7[1:0] (D[7:6])/Port input interrupt select register 2 (0x402C7)
SPTEX7(D[7])/Port input interrupt selection expansion register
(0x40306)
P27
P07
P33
K67
P67
FPT6
SPT6[1:0] (D[5:4])/Port input interrupt select register 2 (0x402C7)
SPTEX6(D[6])/Port input interrupt selection expansion register
(0x40306)
P26
P06
P32
K66
P66
FPT5
SPT5[1:0] (D[3:2])/Port input interrupt select register 2 (0x402C7)
SPTEX5(D[5])/Port input interrupt selection expansion register
(0x40306)
P25
P05
P31
K65
P65
FPT4
SPT4[1:0] (D[1:0])/Port input interrupt select register 2 (0x402C7)
SPTEX4(D[4])/Port input interrupt selection expansion register
(0x40306)
P24
P04
K54
K64
P64
FPT3
SPT3[1:0] (D[7:6])/Port input interrupt select register 1 (0x402C6)
SPTEX3(D[3])/Port input interrupt selection expansion register
(0x40306)
P23
P03
K53
K63
P63
FPT2
SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x402C6)
SPTEX2(D[2])/Port input interrupt selection expansion register
(0x40306)
P22
P02
K52
K62
P62
FPT1
SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x402C6)
SPTEX1(D[1])/Port input interrupt selection expansion register
(0x40306)
P21
P01
K51
K61
P61
FPT0
SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x402C6)
SPTEX0(D[0])/Port input interrupt selection expansion register
(0x40306)
P20
P00
K50
K60
P60
Conditions for port input-interrupt generation
Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the
edge/level select register (0x402C9, 0x40310) is used for this selection. When SEPTx is set to "1", the FPTx
interrupt will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated
by the input signal level.
Furthermore, the signal polarity can be selected using the SPPTx bit of the input porarity select register
(0x402C8, 0x40310).
With these registers, the port input interrupt condition is decided as shown in Table 10.6.
Table 10.6
Port Input Interrupt Condition
SEPTx
SPPTx
FPTx interrupt condition
1
Rising edge
1
0
Falling edge
0
1
High level
0
Low level
When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt
conditions set by the interrupt controller are met, an interrupt is generated.