
III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33T01 FUNCTION PART
EPSON
B-III-8-17
Control and Operation of Asynchronous Transfer
Transmit control
(1)
Enabling transmit operation
Use the transmit-enable bit TXENx for transmit control.
Ch.0 transmit-enable: TXEN0 (D7) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 transmit-enable: TXEN1 (D7) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 transmit-enable: TXEN2 (D7) / Serial I/F Ch.2 control register (0x401E3)
Ch.3 transmit-enable: TXEN3 (D7) / Serial I/F Ch.3 control register (0x401E8)
When transmit is enabled by writing "1" to this bit, the clock input to the shift register is enabled (ready for
input), thus allowing data to be transmitted.
Transmit is disabled by writing "0" to TXENx.
Note: Do not set TXENx to "0" during a transmit operation.
(2)
Transmit procedure
The serial interface has a transmit shift register and a transmit data register (transmit data buffer) that are
provided independently of those used for receive operations.
Ch.0 transmit data: TXD0[7:0] (D[7:0]) / Serial I/F Ch.0 transmit data register (0x401E0)
Ch.1 transmit data: TXD1[7:0] (D[7:0]) / Serial I/F Ch.1 transmit data register (0x401E5)
Ch.2 transmit data: TXD2[7:0] (D[7:0]) / Serial I/F Ch.2 transmit data register (0x401F0)
Ch.3 transmit data: TXD3[7:0] (D[7:0]) / Serial I/F Ch.3 transmit data register (0x401F5)
The serial interface starts a transmit operation by writing data to this register. In the 7-bit asynchronous mode,
bit 7 (MSB) in each register is ignored.
The serial interface also contains a status bit to indicate the status of the transmit data register.
Ch.0 transmit data buffer empty: TDBE0 (D1) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit data buffer empty: TDBE1 (D1) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit data buffer empty: TDBE2 (D1) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit data buffer empty: TDBE3 (D1) / Serial I/F Ch.3 status register (0x401F7)
This bit is reset to "0" by writing data to the transmit data register, and set back to "1" (buffer empty) when the
data is transferred to the shift register. The transfer begins when the serial interface starts sending the start bit.
The transfer status can be checked using the transmit-completion flag (TENDx).
Ch.0 transmit-completion flag: TEND0 (D5) / Serial I/F Ch.0 status register (0x401E2)
Ch.1 transmit-completion flag: TEND1 (D5) / Serial I/F Ch.1 status register (0x401E7)
Ch.2 transmit-completion flag: TEND2 (D5) / Serial I/F Ch.2 status register (0x401F2)
Ch.3 transmit-completion flag: TEND3 (D5) / Serial I/F Ch.3 status register (0x401F7)
This bit goes "1" when data is being transmitted and goes "0" when the transmission has completed.
When data is transmitted successively in asynchronous mode, TENDx maintains "1" until all data is
transmitted.
Figure 8.12 shows a transmit timing chart in the asynchronous mode.
Example: Data length 8 bits
Stop bit
1 bit
Parity bit
Included