
1
OUTLINE
A-8
EPSON
S1C33T01 PRODUCT PART
Table 1.3.3
List of Pins for Internal Peripheral Circuits
Pin name
Pin No.
I/O
I/O Level
Pull-
up
Power
supply
Function
K50
#DMAREQ0
30
I
CMOS
SCHMITT
-
H
K50:
Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1
29
I
CMOS
SCHMITT
-
H
K51:
Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K52
#ADTRG
28
I
CMOS
SCHMITT
-
H
K52:
Input port when CFK52(D2/0x402C0) = "0" (default)
#ADTRG:
A/D converter trigger input when CFK52(D2/0x402C0) = "1"
K53
#DMAREQ2
27
I
CMOS
SCHMITT
-
H
K53:
Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3
26
I
CMOS
SCHMITT
-
H
K54:
Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
K60
AD0
43
I
-
A
K60:
Input port when CFK60(D0/0x402C3) = "0" (default)
AD0:
A/D converter Ch. 0 input when CFK60(D0/0x402C3) = "1"
K61
AD1
42
I
-
A
K61:
Input port when CFK61(D1/0x402C3) = "0" (default)
AD1:
A/D converter Ch. 1 input when CFK61(D1/0x402C3) = "1"
K62
AD2
41
I
-
A
K62:
Input port when CFK62(D2/0x402C3) = "0" (default)
AD2:
A/D converter Ch. 2 input when CFK62(D2/0x402C3) = "1"
K63
AD3
40
I
-
A
K63:
Input port when CFK63(D3/0x402C3) = "0" (default)
AD3:
A/D converter Ch. 3 input when CFK63(D3/0x402C3) = "1"
K64
AD4
39
I
-
A
K64:
Input port when CFK64(D4/0x402C3) = "0" (default)
AD4:
A/D converter Ch. 4 input when CFK64(D4/0x402C3) = "1"
K65
AD5
38
I
-
A
K65:
Input port when CFK65(D5/0x402C3) = "0" (default)
AD5:
A/D converter Ch. 5 input when CFK65(D5/0x402C3) = "1"
K66
AD6
37
I
-
A
K66:
Input port when CFK66(D6/0x402C3) = "0" (default)
AD6:
A/D converter Ch. 6 input when CFK60(D6/0x402C3) = "1"
K67
AD7
36
I
-
A
K67:
Input port when CFK67(D7/0x402C3) = "0" (default)
AD7:
A/D converter Ch. 7 input when CFK67(D7/0x402C3) = "1"
P00
SIN0
22
I/O CMOS/LVTTL
SCHMITT
-
H
P00:
I/O port when CFP00(D0/0x402D0) = "0" (default)
SIN0:
Serial I/F Ch. 0 data input when CFP00(D0/0x402D0) = "1"
P01
SOUT0
21
I/O CMOS/LVTTL
SCHMITT
-
H
P01:
I/O port when CFP01(D1/0x402D0) = "0" (default)
SOUT0:
Serial I/F Ch. 0 data output when CFP01(D1/0x402D0) = "1"
P02
#SCLK0
20
I/O CMOS/LVTTL
SCHMITT
-
H
P02:
I/O port when CFP02(D2/0x402D0) = "0" (default)
#SCLK0:
Serial I/F Ch. 0 clock input/output when CFP02(D2/0x402D0)
= "1"
P03
#SRDY0
19
I/O CMOS/LVTTL
SCHMITT
-
H
P03:
I/O port when CFP03(D3/0x402D0) = "0" (default)
#SRDY0:
Serial I/F Ch. 0 ready signal output
when CFP03(D3/0x402D0) = "1"
P04
SIN1
#DMAACK2
17
I/O CMOS/LVTTL
SCHMITT
-
H
P04:
I/O port when CFP04(D4/0x402D0) = "0"
and CFEX4(D4/0x402DF) = "0" (default)
SIN1:
Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1"
and CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output
when CFEX4(D4/0x402DF) = "1"
P05
SOUT1
#DMAEND2
16
I/O CMOS/LVTTL
SCHMITT
-
H
P05:
I/O port when CFP05(D5/0x402D0) = "0"
and CFEX5(D5/0x402DF) = "0" (default)
SOUT1:
Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1"
and CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal output
when CFEX5(D5/0x402DF) = "1"
P06
#SCLK1
#DMAACK3
15
I/O CMOS/LVTTL
SCHMITT
-
H
P06:
I/O port when CFP06(D6/0x402D0) = "0"
and CFEX6(D6/0x402DF) = "0" (default)
#SCLK1:
Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0)
= "1" and CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output
when CFEX6(D6/0x402DF) = "1"