
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33T01 FUNCTION PART
EPSON
B-III-4-11
Intelligent DMA
The interrupt factor of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory
DMA transfers to be performed cyclically.
The following shows the IDMA channel numbers set for each interrupt factor of timer:
IDMA Ch.
Timer 0 comparison B:
0x07
Timer 0 comparison A:
0x08
Timer 1 comparison B:
0x09
Timer 1 comparison A:
0x0A
Timer 2 comparison B:
0x0B
Timer 2 comparison A:
0x0C
Timer 3 comparison B:
0x0D
Timer 3 comparison A:
0x0E
Timer 4 comparison B:
0x0F
Timer 4 comparison A:
0x10
Timer 5 comparison B:
0x11
Timer 5 comparison A:
0x12
Timer 6 comparison B:
0x2E
Timer 6 comparison A:
0x2F
Timer 7 comparison B:
0x30
Timer 7 comparison A:
0x31
Timer 8 comparison B:
0x32
Timer 8 comparison A:
0x33
Timer 9 comparison B:
0x34
Timer 9 comparison A:
0x35
For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table 4.5 must be set to "1" in advance.
Transfer conditions, etc. must also be set on the IDMA side in advance.
Table 4.5
Control Bits for IDMA Transfer
Interrupt factor
IDMA request bit
IDMA enable bit
Timer 0 comparison A
R16TC0(D7/0x40290)
DE16TC0(D7/0x40294)
Timer 0 comparison B
R16TU0(D6/0x40290)
DE16TU0(D6/0x40294)
Timer 1 comparison A
R16TC1(D1/0x40291)
DE16TC1(D1/0x40295)
Timer 1 comparison B
R16TU1(D0/0x40291)
DE16TU1(D0/0x40295)
Timer 2 comparison A
R16TC2(D3/0x40291)
DE16TC2(D3/0x40295)
Timer 2 comparison B
R16TU2(D2/0x40291)
DE16TU2(D2/0x40295)
Timer 3 comparison A
R16TC3(D5/0x40291)
DE16TC3(D5/0x40295)
Timer 3 comparison B
R16TU3(D4/0x40291)
DE16TU3(D4/0x40295)
Timer 4 comparison A
R16TC4(D7/0x40291)
DE16TC4(D7/0x40295)
Timer 4 comparison B
R16TU4(D6/0x40291)
DE16TU4(D6/0x40295)
Timer 5 comparison A
R16TC5(D1/0x40292)
DE16TC5(D1/0x40296)
Timer 5 comparison B
R16TU5(D0/0x40292)
DE16TU5(D0/0x40296)
Timer 6 comparison A
R16TC6(D1/0x402AD)
DE16TC6(D1/0x402AF)
Timer 6 comparison B
R16TU6(D0/0x402AD)
DE16TU6(D0/0x402AF)
Timer 7 comparison A
R16TC7(D3/0x402AD)
DE16TC7(D3/0x402AF)
Timer 7 comparison B
R16TU7(D2/0x402AD)
DE16TU7(D2/0x402AF)
Timer 8 comparison A
R16TC8(D5/0x402AD)
DE16TC8(D5/0x402AF)
Timer 8 comparison B
R16TU8(D4/0x402AD)
DE16TU8(D4/0x402AF)
Timer 9 comparison A
R16TC9(D7/0x402AD)
DE16TC9(D7/0x402AF)
Timer 9 comparison B
R16TU9(D6/0x402AD)
DE16TU9(D6/0x402AF)
If the IDMA request and enable bits are set to "1", IDMA is invoked through generation of an interrupt factor.
No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is
completed. The registers can also be set so as not to generate an interrupt,with only a DMA transfer performed.
For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to "IDMA
(Intelligent DMA)".