
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
B-III-10-10
EPSON
S1C33T01 FUNCTION PART
Table 10.4
Control Bits of I/O Ports (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
CFP87
CFP86
CFP85
CFP84
CFP83
CFP82
CFP81
CFP80
D7
D6
D5
D4
D3
D2
D1
D0
P87 function selection
P86 function selection
P85 function selection
P84 function selection
P83 function selection
P82 function selection
P81 function selection
P80 function selection
0
R/W
004030D
(B)
1 TM9
0 P87
1 TM8
0 P86
1 TM7
0 P85
1 TM6
0 P84
1 EXCL9
0 P83
1 EXCL8
0 P82
1 EXCL7
0 P81
1 EXCL6
0 P80
P8 function
select register
P87D
P86D
P85D
P84D
P83D
P82D
P81D
P80D
D7
D6
D5
D4
D3
D2
D1
D0
P87 I/O port data
P86 I/O port data
P85 I/O port data
P84 I/O port data
P83 I/O port data
P82 I/O port data
P81 I/O port data
P80 I/O port data
0
R/W
004030E
(B)
1 High
0 Low
P8 I/O port data
register
IOC87
IOC86
IOC85
IOC84
IOC83
IOC82
IOC81
IOC80
D7
D6
D5
D4
D3
D2
D1
D0
P87 I/O control
P86 I/O control
P85 I/O control
P84 I/O control
P83 I/O control
P82 I/O control
P81 I/O control
P80 I/O control
0
R/W
004030F
(B)
1 Output
0 Input
P8 I/O control
register
CFP07–CFP00: P0[7:0] function selection (D[7:0]) / P0 function select register (0x402D0)
CFP16–CFP10: P1[6:0] function selection (D[6:0]) / P1 function select register (0x402D4)
CFP27–CFP20: P2[7:0] function selection (D[7:0]) / P2 function select register (0x402D8)
CFP35–CFP30: P3[5:0] function selection (D[5:0]) / P3 function select register (0x402DC)
CFP47–CFP40: P4[7:0] function selection (D[7:0]) / P4 function select register (0x40300)
CFP57–CFP50: P5[7:0] function selection (D[7:0]) / P5 function select register (0x40303)
CFP71–CFP70: P7[1:0] function selection (D[7:0]) / P7 function select register (0x4030A)
CFP87–CFP80: P8[7:0] function selection (D[7:0]) / P8 function select register (0x4030D)
Selects the function of each I/O port pin.
Write "1": Used for peripheral circuit
Write "0": I/O port pin
Read: Valid
When a bit of the CFP register is set to "1", the corresponding pin is set for use with peripheral circuits (see Table
10.3). The pins for which register bits are set to "0" can be used as general-purpose I/O ports.
At cold start, CFP is set to "0" (I/O port). At hot start, CFP retains its state from prior to the initial reset.
P07D–P00D: P0[7:0] I/O port data (D[7:0]) / P0 I/O port data register (0x402D1)
P16D–P10D: P1[6:0] I/O port data (D[6:0]) / P1 I/O port data register (0x402D5)
P27D–P20D: P2[7:0] I/O port data (D[7:0]) / P2 I/O port data register (0x402D9)
P35D–P30D: P3[5:0] I/O port data (D[5:0]) / P3 I/O port data register (0x402DD)
P47D–P40D: P4[7:0] I/O port data (D[7:0]) / P4 I/O port data register (0x40301)
P57D–P50D: P5[7:0] I/O port data (D[7:0]) / P5 I/O port data register (0x40304)
P67D–P60D: P6[7:0] I/O port data (D[7:0]) / P6 I/O port data register (0x40307)
P77D–P70D: P7[7:0] I/O port data (D[7:0]) / P7 I/O port data register (0x4030B)
P87D–P80D: P8[7:0] I/O port data (D[7:0]) / P8 I/O port data register (0x4030E)
This register reads data from I/O-port pins or sets output data.
When writing data
Write "1": High level
Write "0": Low level
When an I/O port is set for output, the data written to it is directly output to the I/O port pin. If the data written to the
port is "1", the port pin is set high (VDD, VDDE level); if the data is "0", the port pin is set low (VSS level).