
III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33T01 FUNCTION PART
EPSON
B-III-8-25
When the interrupt factor described above occurs, the corresponding interrupt factor flag is set to "1". If the
interrupt enable register bit for that interrupt factor has been set to "1", an interrupt request is generated.
Interrupts caused by an interrupt factor can be disabled by leaving the interrupt enable register bit for that factor
set to "0". The interrupt factor flag is set to "1" whenever interrupt conditions are met, regardless of the setting
of the interrupt enable register (even if it is set to "0").
The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and
7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has
been generated.
In addition, only when the PSR's IE bit = "1" (interrupts enabled) and the set value of the IL is smaller than the
input interrupt level set by the interrupt priority register, will the input interrupt request actually be accepted by
the CPU.
For details on these interrupt control registers, as well as the device operation when an interrupt has occurred,
refer to "ITC (Interrupt Controller)".
Intelligent DMA
The receive-buffer full interrupt and transmit-buffer empty interrupt factors can be used to invoke intelligent
DMA (IDMA). This enables successive transmit/receive operations between memory and the
transmit/receive-buffer to be performed by means of a DAM transfer.
The following shows the IDMA channel numbers set for each interrupt factor:
IDMA Ch.
Ch.0 receive-buffer full interrupt:
0x17
Ch.0 transmit-buffer empty interrupt: 0x18
Ch.1 receive-buffer full interrupt:
0x19
Ch.1 transmit-buffer empty interrupt: 0x1A
Ch.2 receive-buffer full interrupt:
0x22
Ch.2 transmit-buffer empty interrupt: 0x23
Ch.3 receive-buffer full interrupt:
0x24
Ch.3 transmit-buffer empty interrupt: 0x25
The IDMA request and enable bits shown in Table 8.8 must be set to "1" for IDMA to be invoked. Transfer
conditions, etc. on the IDMA side must also be set in advance.
Table 8.8
Control Bits for IDMA Transfer
Channel
Interrupt factor
IDMA request bit
IDMA enable bit
Ch.0
Receive-buffer full
RSRX0(D6/0x40292)
DESRX0(D6/0x40296)
Transmit-buffer empty
RSTX0(D7/0x40292)
DESTX0(D7/0x40296)
Ch.1
Receive-buffer full
RSRX1(D0/0x40293)
DESRX1(D0/0x40297)
Transmit-buffer empty
RSTX1(D1/0x40293)
DESTX1(D1/0x40297)
Ch.2
Receive-buffer full
RSRX2(D2/0x4029B)
DESRX2(D2/0x4029C)
Transmit-buffer empty
RSTX2(D3/0x4029B)
DESTX2(D3/0x4029C)
Ch.3
Receive-buffer full
RSRX3(D4/0x4029B)
DESRX3(D4/0x4029C)
Transmit-buffer empty
RSTX3(D5/0x4029B)
DESTX3(D5/0x4029C)
If an interrupt factor occurs when the IDMA request and enable bits are set to "1", IDMA is invoked. No
interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA
transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed.
For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to "IDMA
(Intelligent DMA)".
High-speed DMA
The serial interface Ch.0 and Ch. 1 transmit buffer empty and receive buffer full interrupt factors can be used to
start high-speed DMS (HSDMA) operations.
The following shows the HSDMA channel number and trigger set-up bit corresponding to each channel: