
II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-20
EPSON
S1C33T01 FUNCTION PART
Table 5.3
Control Bits of Interrupt Controller (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
–
F16TC9
F16TU9
–
F16TC8
F16TU8
–
D7
D6
D5–4
D3
D2
D1–0
16-bit timer 9 comparison A
16-bit timer 9 comparison B
reserved
16-bit timer 8 comparison A
16-bit timer 8 comparison B
reserved
0
–
0
–
R/W
–
R/W
–
0 when being read.
00402AB
(B)
1 Factor is
generated
0 No factor is
generated
1 Factor is
generated
0 No factor is
generated
16-bit timer 8/9
interrupt factor
flag register
RP15
RP14
RP13
RP12
RP11
RP10
RP9
RP8
D7
D6
D5
D4
D3
D2
D1
D0
Port input 15
Port input 14
Port input 13
Port input 12
Port input 11
Port input 10
Port input 9
Port input 8
0
R/W
00402AC
(B)
1 IDMA
request
0 Interrupt
request
Port input
IDMA request
register
R16TC9
R16TU9
R16TC8
R16TU8
R16TC7
R16TU7
R16TC6
R16TU6
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 9 comparison A
16-bit timer 9 comparison B
16-bit timer 8 comparison A
16-bit timer 8 comparison B
16-bit timer 7 comparison A
16-bit timer 7 comparison B
16-bit timer 6 comparison A
16-bit timer 6 comparison B
0
R/W
00402AD
(B)
1 IDMA
request
0 Interrupt
request
16-bit timer 6-9
IDMA request
register
DEP15
DEP14
DEP13
DEP12
DEP11
DEP10
DEP9
DEP8
D7
D6
D5
D4
D3
D2
D1
D0
Port input 15
Port input 14
Port input 13
Port input 12
Port input 11
Port input 10
Port input 9
Port input 8
0
R/W
00402AE
(B)
1 IDMA
enabled
0 IDMA
disabled
Port input
IDMA enable
register
DE16TC9
DE16TU9
DE16TC8
DE16TU8
DE16TC7
DE16TU7
DE16TC6
DE16TU6
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 9 comparison A
16-bit timer 9 comparison B
16-bit timer 8 comparison A
16-bit timer 8 comparison B
16-bit timer 7 comparison A
16-bit timer 7 comparison B
16-bit timer 6 comparison A
16-bit timer 6 comparison B
0
R/W
00402AF
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 6-9
IDMA enable
register
–
0 to 7
–
–
P12C12
P12C11
P12C10
–
P12C02
P12C01
P12C00
D7
D6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1
interrupt level
reserved
I2CSMST Ch.0
interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
00402B0
(B)
Single-master
I2C-bus Ch.0/1
interrupt
priority
register
–
E12CW1
E12CR1
E12CI1
E12CW0
E12CR0
E12CI0
D7–6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMA request
I2CSMST Ch.1 request
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
I2CSMST Ch.0 request
–
0
–
R/W
0 when being read.
00402B1
(B)
1 Enabled
0 Disabled
Single-master
I2C-bus Ch.0/1
interrupt
ebable
register
–
F12CW1
F12CR1
F12CI1
F12CW0
F12CR0
F12CI0
D7–6
D5
D4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMA request
I2CSMST Ch.1 request
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
I2CSMST Ch.0 request
–
0
–
R/W
0 when being read.
00402B2
(B)
1 Factor is
generated
0 No factor is
generated
Single-master
I2C-bus Ch.0/1
interrupt
factor flag
register
–
R12CW1
R12CR1
R12CW0
R12CR0
D7–4
D3
D2
D1
D0
reserved
I2CSMST Ch.1 write DMA request
I2CSMST Ch.1 read DMArequest
I2CSMST Ch.0 write DMA request
I2CSMST Ch.0 read DMA request
–
0
–
R/W
0 when being read.
00402B3
(B)
–
1 IDMA
request
0 Interrupt
request
Single-master
I2C-bus Ch.0/1
IDMA
request
register