
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-6
EPSON
S1C33T01 FUNCTION PART
Timer 8 comparison data B: CR8B[15:0] (D[F:0]) / 16-bit timer 8 comparison B set-up register (0x481C2)
Timer 9 comparison data A: CR9A[15:0] (D[F:0]) / 16-bit timer 9 comparison A set-up register (0x481C8)
Timer 9 comparison data B: CR9B[15:0] (D[F:0]) / 16-bit timer 9 comparison B set-up register (0x481CA)
When SELCRBx is set to "0", these registers allow direct reading/writing from/to the comparison data register.
When SELCRBx is set to "1", these registers are used to read/write from/to the comparison register buffer.The
content of the buffer is loaded to the comparison data register when the counter is reset.
At initial reset, the comparison data registers/buffers are not initialized.
The programmable timer compares the comparison data register and count data and, when the two values are
equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx
signal) to external devices, in addition to generating an interrupt.
The comparison data B is also used to reset the counter.
Resetting the counter
Each timer includes the PRESETx bit to reset the counter.
Timer 0 reset: PRESET0 (D1) / 16-bit timer 0 control register (0x48186)
Timer 1 reset: PRESET1 (D1) / 16-bit timer 1 control register (0x4818E)
Timer 2 reset: PRESET2 (D1) / 16-bit timer 2 control register (0x48196)
Timer 3 reset: PRESET3 (D1) / 16-bit timer 3 control register (0x4819E)
Timer 4 reset: PRESET4 (D1) / 16-bit timer 4 control register (0x481A6)
Timer 5 reset: PRESET5 (D1) / 16-bit timer 5 control register (0x481AE)
Timer 6 reset: PRESET6 (D1) / 16-bit timer 6 control register (0x481B6)
Timer 7 reset: PRESET7 (D1) / 16-bit timer 7 control register (0x481BE)
Timer 8 reset: PRESET8 (D1) / 16-bit timer 8 control register (0x481C6)
Timer 9 reset: PRESET9 (D1) / 16-bit timer 9 control register (0x481CE)
Normally, reset the counter before starting count-up by writing "1" to this control bit.
After the counter starts counting, it will be reset by comparison match B.
Timer RUN/STOP control
Each timer includes the PRUNx bit to control RUN/STOP.
Timer 0 RUN/STOP control: PRUN0 (D0) / 16-bit timer 0 control register (0x48186)
Timer 1 RUN/STOP control: PRUN1 (D0) / 16-bit timer 1 control register (0x4818E)
Timer 2 RUN/STOP control: PRUN2 (D0) / 16-bit timer 2 control register (0x48196)
Timer 3 RUN/STOP control: PRUN3 (D0) / 16-bit timer 3 control register (0x4819E)
Timer 4 RUN/STOP control: PRUN4 (D0) / 16-bit timer 4 control register (0x481A6)
Timer 5 RUN/STOP control: PRUN5 (D0) / 16-bit timer 5 control register (0x481AE)
Timer 6 RUN/STOP control: PRUN6 (D0) / 16-bit timer 6 control register (0x481B6)
Timer 7 RUN/STOP control: PRUN7 (D0) / 16-bit timer 7 control register (0x481BE)
Timer 8 RUN/STOP control: PRUN8 (D0) / 16-bit timer 8 control register (0x481C6)
Timer 9 RUN/STOP control: PRUN9 (D0) / 16-bit timer 9 control register (0x481CE)
The timer starts counting when "1" is written to PRUNx. The clock input is disabled and the timer stops
counting when "0" is written to PRUNx.
This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the
counter retains its count so that the timer can start counting again from that point.
If the count of the counter matches the set value of the comparison data register during count-up, the timer
generates a comparison match interrupt.
When the counter matches comparison data B, an interrupt is generated and the counter is reset. At the same
time, the values set in the compare register buffer are loaded to the compare data register if SELCRBx is set to
"1".
The counter continues counting up regardless of which interrupt has occurred. In the case of a comparison B
interrupt, the counter starts counting beginning with 0.
When both the timer RUN/STOP control bit (PRUNx) and the timer reset bit (PRESETx) are set to "1" at the
same time, the timer starts counting after resetting the counter.