
II CORE BLOCK: ITC (Interrupt Controller)
S1C33T01 FUNCTION PART
EPSON
B-II-5-17
Table 5.3
Control Bits of Interrupt Controller (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
RP7
RP6
RP5
RP4
–
RADE
RSTX1
RSRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
–
0
R/W
–
R/W
0 when being read.
0040293
(B)
1 IDMA
request
0 Interrupt
request
1 IDMA
request
0 Interrupt
request
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
0040294
(B)
1 IDMA
enabled
0 IDMA
disabled
Port input 0–3,
high-speed
DMA, 16-bit
timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
R/W
0040295
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
R/W
0040296
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
DEP7
DEP6
DEP5
DEP4
–
DEADE
DESTX1
DESRX1
D7
D6
D5
D4
D3
D2
D1
D0
Port input 7
Port input 6
Port input 5
Port input 4
reserved
A/D converter
SIF Ch.1 transmit buffer empty
SIF Ch.1 receive buffer full
0
–
0
R/W
–
R/W
0 when being read.
0040297
(B)
1 IDMA
enabled
0 IDMA
disabled
1 IDMA
enabled
0 IDMA
disabled
–
Serial I/F Ch.1,
A/D,
port input 4–7
IDMA enable
register
HSD1S3
HSD1S2
HSD1S1
HSD1S0
HSD0S3
HSD0S2
HSD0S1
HSD0S0
D7
D6
D5
D4
D3
D2
D1
D0
High-speed DMA Ch.1
trigger set-up
High-speed DMA Ch.0
trigger set-up
0
R/W
0040298
(B)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Software trigger
K51 input (falling edge)
K51 input (rising edge)
Port 1 input
Port 5 input
8-bit timer Ch.1 underflow
16-bit timer Ch.1 compare B
16-bit timer Ch.1 compare A
16-bit timer Ch.5 compare B
16-bit timer Ch.5 compare A
SI/F Ch.1 Rx buffer full
SI/F Ch.1 Tx buffer empty
A/D conversion completion
Single-master I2C-bus Ch.1 read DMA request
Single-master I2C-bus Ch.1 write DMA request
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Software trigger
K50 input (falling edge)
K50 input (rising edge)
Port 0 input
Port 4 input
8-bit timer Ch.0 underflow
16-bit timer Ch.0 compare B
16-bit timer Ch.0 compare A
16-bit timer Ch.4 compare B
16-bit timer Ch.4 compare A
SI/F Ch.0 Rx buffer full
SI/F Ch.0 Tx buffer empty
A/D conversion completion
Single-master I2C-bus Ch.0 read DMA request
Single-master I2C-bus Ch.0 write DMA request
High-speed
DMA Ch.0/1
trigger set-up
register