
4
PERIPHERAL CIRCUITS
A-54
EPSON
S1C33T01 PRODUCT PART
Table 4.2.1
I/O Memory Map (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
TTBR33
TTBR32
TTBR31
TTBR30
TTBR2B
TTBR2A
TTBR29
TTBR28
TTBR27
TTBR26
TTBR25
TTBR24
TTBR23
TTBR22
TTBR21
TTBR20
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Trap table base address [31:28]
Trap table base address [27:16]
Fixed at 0
The initial value is set.
0x0C0
0
1
0
R
R/W
0 when being read.
Writing 1 not allowed.
0048136
(HW)
TTBR high-
order register
–
1 Enabled
0 Disabled
1 Enabled
0 Disabled
A18AS
A16AS
A14AS
A12AS
–
A8AS
A6AS
A5AS
A18RD
A16RD
A14RD
A12RD
–
A8RD
A6RD
A5RD
DF
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Area 18, 17 address strobe signal
Area 16, 15 address strobe signal
Area 14, 13 address strobe signal
Area 12, 11 address strobe signal
reserved
Area 8, 7 address strobe signal
Area 6 address strobe signal
Area 5, 4 address strobe signal
Area 18, 17 read signal
Area 16, 15 read signal
Area 14, 13 read signal
Area 12, 11 read signal
reserved
Area 8, 7 read signal
Area 6 read signal
Area 5, 4 read signal
0
R/W
–
R/W
–
R/W
0 when being read.
0048138
(HW)
G/A read signal
control register
–
1 Enabled
0 Disabled
1 Enabled
0 Disabled
–
A1X1MD
–
BCLKSEL1
BCLKSEL0
D7–4
D3
D2
D1
D0
reserved
Area 1 access-speed
reserved
BCLK output clock selection
1
0
1
0
1
0
BCLKSEL[1:0]
–
BCLK
PLL_CLK
OSC3_CLK
BCU_CLK
CPU_CLK
0
–
R/W
–
R/W
0 when being read.
x2 speed mode only
0 when being read.
004813A
(B)
BCLK select
register
1 2 cycles
0 4 cycles
A18RH
A16RH
A14RH
A12RH
-
A8RH
A6RH
A5RH
D7
D6
D5
D4
D3
D2
D1
D0
Area 17, 18 read hold cycle
Area 15, 16 read hold cycle
Area 13, 14 read hold cycle
Area 11, 12 read hold cycle
reserved
Area 7, 8 read hold cycle
Area 6 read hold cycle
Area 5 read hold cycle
0
–
0
R/W
–
R/W
Undefined when being read.
004813C
(B)
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
1 Inserted
0 Not inserted
Read cycle
hold time
control
register
–
A18BS
A16BS
A14BS
A12BS
A10BS
A8BS
A6BS
A5BS
D7
D6
D5
D4
D3
D2
D1
D0
Area 17, 18 bus speed selection
Area 15, 16 bus speed selection
Area 13, 14 bus speed selection
Area 11, 12 bus speed selection
reserved
Area 7, 8 bus speed selection
Area 6 bus speed selection
Area 5 bus speed selection
0
R/W
This register's setting
is meaningful when
#x2SPD = 0 (2
×
speed mode)
004813E
(B)
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
1
×1 speed
0 #
×2SPD
Bus speed
setting
register