
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
B-III-4-14
EPSON
S1C33T01 FUNCTION PART
Table 4.7
Control Bits of 16-Bit Programmable Timer (continue)
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
R16TC0
R16TU0
RHDM1
RHDM0
RP3
RP2
RP1
RP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
0040290
(B)
1 IDMA
request
0 Interrupt
request
Port input 0–3,
high-speed
DMA, 16-bit
timer 0
IDMA request
register
R16TC4
R16TU4
R16TC3
R16TU3
R16TC2
R16TU2
R16TC1
R16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
R/W
0040291
(B)
1 IDMA
request
0 Interrupt
request
16-bit timer 1–4
IDMA request
register
RSTX0
RSRX0
R8TU3
R8TU2
R8TU1
R8TU0
R16TC5
R16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
R/W
0040292
(B)
1 IDMA
request
0 Interrupt
request
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA request
register
DE16TC0
DE16TU0
DEHDM1
DEHDM0
DEP3
DEP2
DEP1
DEP0
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 0 comparison A
16-bit timer 0 comparison B
High-speed DMA Ch.1
High-speed DMA Ch.0
Port input 3
Port input 2
Port input 1
Port input 0
0
R/W
0040294
(B)
1 IDMA
enabled
0 IDMA
disabled
Port input 0–3,
high-speed
DMA, 16-bit
timer 0
IDMA enable
register
DE16TC4
DE16TU4
DE16TC3
DE16TU3
DE16TC2
DE16TU2
DE16TC1
DE16TU1
D7
D6
D5
D4
D3
D2
D1
D0
16-bit timer 4 comparison A
16-bit timer 4 comparison B
16-bit timer 3 comparison A
16-bit timer 3 comparison B
16-bit timer 2 comparison A
16-bit timer 2 comparison B
16-bit timer 1 comparison A
16-bit timer 1 comparison B
0
R/W
0040295
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 1–4
IDMA enable
register
DESTX0
DESRX0
DE8TU3
DE8TU2
DE8TU1
DE8TU0
DE16TC5
DE16TU5
D7
D6
D5
D4
D3
D2
D1
D0
SIF Ch.0 transmit buffer empty
SIF Ch.0 receive buffer full
8-bit timer 3 underflow
8-bit timer 2 underflow
8-bit timer 1 underflow
8-bit timer 0 underflow
16-bit timer 5 comparison A
16-bit timer 5 comparison B
0
R/W
0040296
(B)
1 IDMA
enabled
0 IDMA
disabled
16-bit timer 5,
8-bit timer,
serial I/F Ch.0
IDMA enable
register
–
0 to 7
–
–
P16T72
P16T71
P16T70
–
P16T62
P16T61
P16T60
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 7 interrupt level
reserved
16-bit timer 6 interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
00402A4
(B)
16-bit timer 6/7
interrupt
priority register
–
0 to 7
–
–
P16T72
P16T71
P16T70
–
P16T62
P16T61
P16T60
D7
D6
D5
D4
D3
D2
D1
D0
reserved
16-bit timer 9 interrupt level
reserved
16-bit timer 8 interrupt level
–
X
–
X
–
R/W
–
R/W
0 when being read.
00402A5
(B)
16-bit timer 8/9
interrupt
priority register