
III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
S1C33T01 FUNCTION PART
EPSON
B-III-4-27
Write "0": Normal output
Read: Valid
When SELFMx is set to "1", clock output is set in fine mode which allows adjustment of the output signal duty ratio
in units of a half cycle for the input clock.
When SELFMx is set to "0", normal clock output will be performed.
At initial reset, SELCFMx is set to "0" (normal output).
SELCRB0: Timer 0 comparison register buffer enable (D5) / 16-bit timer 0 control register (0x48186)
SELCRB1: Timer 1 comparison register buffer enable (D5) / 16-bit timer 1 control register (0x4818E)
SELCRB2: Timer 2 comparison register buffer enable (D5) / 16-bit timer 2 control register (0x48196)
SELCRB3: Timer 3 comparison register buffer enable (D5) / 16-bit timer 3 control register (0x4819E)
SELCRB4: Timer 4 comparison register buffer enable (D5) / 16-bit timer 4 control register (0x481A6)
SELCRB5: Timer 5 comparison register buffer enable (D5) / 16-bit timer 5 control register (0x481AE)
SELCRB6: Timer 6 comparison register buffer enable (D5) / 16-bit timer 6 control register (0x481B6)
SELCRB7: Timer 7 comparison register buffer enable (D5) / 16-bit timer 7 control register (0x481BE)
SELCRB8: Timer 8 comparison register buffer enable (D5) / 16-bit timer 8 control register (0x481C6)
SELCRB9: Timer 9 comparison register buffer enable (D5) / 16-bit timer 9 control register (0x481CE)
Enables or disables writing to the comparison register buffer.
Write "1": Enabled
Write "0": Disabled
Read: Valid
When SELCRBx is set to "1", comparison data is read and written from/to the comparison register buffer. The
content of the buffer is loaded to the comparison data register when the counter is reset by the software or the
comparison B signal.
When SELCRBx is set to "0", comparison data is read and written from/to the comparison data register.
At initial reset, SELCRBx is set to "0" (disabled).
OUTINV0: Timer 0 output inversion (D4) / 16-bit timer 0 control register (0x48186)
OUTINV1: Timer 1 output inversion (D4) / 16-bit timer 1 control register (0x4818E)
OUTINV2: Timer 2 output inversion (D4) / 16-bit timer 2 control register (0x48196)
OUTINV3: Timer 3 output inversion (D4) / 16-bit timer 3 control register (0x4819E)
OUTINV4: Timer 4 output inversion (D4) / 16-bit timer 4 control register (0x481A6)
OUTINV5: Timer 5 output inversion (D4) / 16-bit timer 5 control register (0x481AE)
OUTINV6: Timer 6 output inversion (D4) / 16-bit timer 6 control register (0x481B6)
OUTINV7: Timer 7 output inversion (D4) / 16-bit timer 7 control register (0x481BE)
OUTINV8: Timer 8 output inversion (D4) / 16-bit timer 8 control register (0x481C6)
OUTINV9: Timer 9 output inversion (D4) / 16-bit timer 9 control register (0x481CE)
Selects a logic of the output signal.
Write "1": Inverted (active low)
Write "0": Normal (active high)
Read: Valid
By writing "1" to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When
OUTINVx is set to "0", an active-high signal (off level = low) is generated.
At initial reset, OUTINVx is set to "0" (normal).