
II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-2
EPSON
S1C33T01 FUNCTION PART
Table 5.1
List of Maskable Interrupts (continue)
No.
HEX
No.
Vector number
(Hex address)
Interrupt system
(Peripheral circuit)
Interrupt factor
IDMA
Ch.
Priority
–
63
reserved
–
High
34
40 64(Base+100)
A/D converter
A/D converter, end of conversion
27
↑
35
41 65(Base+104)
Clock timer
Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
–
1-minuet, 1-hour or specified time count up
–
66–67
reserved
–
36
44 68(Base+110)
Port input interrupt 4
Edge (rising or falling) or level (High or Low)
28
37
45 69(Base+114)
Port input interrupt 5
Edge (rising or falling) or level (High or Low)
29
38
46 70(Base+118)
Port input interrupt 6
Edge (rising or falling) or level (High or Low)
30
39
47 71(Base+11C)
Port input interrupt 7
Edge (rising or falling) or level (High or Low)
31
40
48 72(Base+120)
8-bit programmable timer
Timer 4 underflow
32
41
49 73(Base+124)
Timer 5 underflow
33
–
74-75
–
42
4C 76(Base+130)
Serial interface Ch.2
Receive error
–
43
4D 77(Base+134)
Receive buffer full
34
44
4E 78(Base+138)
Transmit buffer empty
35
–
79
reserved
–
45
50 80(Base+140)
Serial interface Ch.3
Receive error
–
46
51 81(Base+144)
Receive buffer full
36
47
52 82(Base+148)
Transmit buffer empty
37
–
83
reserved
–
48
54 84(Base+150)
Port input interrupt 8
Edge (rising or falling) or level (High or Low)
38
49
55 85(Base+154)
Port input interrupt 9
Edge (rising or falling) or level (High or Low)
39
50
56 86(Base+158)
Port input interrupt 10
Edge (rising or falling) or level (High or Low)
40
51
57 87(Base+15C)
Port input interrupt 11
Edge (rising or falling) or level (High or Low)
41
52
58 88(Base+160)
Port input interrupt 12
Edge (rising or falling) or level (High or Low)
42
53
59 89(Base+164)
Port input interrupt 13
Edge (rising or falling) or level (High or Low)
43
54
5A 90(Base+168)
Port input interrupt 14
Edge (rising or falling) or level (High or Low)
44
55
5B 91(Base+16C)
Port input interrupt 15
Edge (rising or falling) or level (High or Low)
45
–
92-93
reserved
–
56
5E 94(Base+178)
8-bit programmable timer 6
Timer 6 comparison B
46
57
5F 95(Base+17C)
Timer 6 comparison A
47
–
96-97
reserved
–
58
62 98(Base+188)
16-bit programmable timer 7
Timer 7 comparison B
48
59
63 99(Base+18C)
Timer 7 comparison A
49
–
100-101
reserved
–
60
66 102(Base+198) 16-bit programmable timer 8
Timer 8 comparison B
50
61
67 103(Base+19C)
Timer 8 comparison A
51
–
104-105
reserved
–
62
6A 106(Base+198) 16-bit programmable timer 9
Timer 9 comparison B
52
63
6B 107(Base+19C)
Timer 9 comparison A
53
64
6C 108(Base+198) Single-master I
2C-bus Ch. 0
Command complete/error occurred
–
65
6D 109(Base+19C)
Read DMA request
54
66
6E 110(Base+198)
Write DMA request
55
–
111
reserved
–
67
70 112(Base+1C0) Single-master I
2C-bus Ch. 1
Command complete/error occurred
–
68
71 113(Base+1C4)
Read DMA request
56
69
72 114(Base+1C8)
Write DMA request
57
↓
–
115
reserved
–
Low