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參數(shù)資料
| 型號： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 74/327頁 |
| 文件大小： | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
11-14
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
reset the PCI to Add-On or Add-On to PCI FIFO
flags. The FIFO flags can always be reset with soft-
ware through the Add-On General Control/Status
Register (AGCSTS) or the Bus Master Control/Status
Register (MCSR), but these hardware inputs are use-
ful for designs which do no implement a CPU on the
Add-On card. Asserting the FRC# input resets the
PCI to Add-On FIFO. Asserting the FWC# input re-
sets the Add-On to PCI FIFO.
The AMREN and AMWEN inputs allow Add-On logic to
individually enable and disable bus mastering for the
PCI to Add-On and Add-On to PCI FIFO. These inputs
override the Bus Master Control/Status Register
(MCSR) bus master enable bits. The S5933 may re-
quest the PCI bus for the PCI to Add-On FIFO when
AMREN is asserted and may request the PCI bus for
the Add-On to PCI FIFO when AMWEN is asserted. If
AMREN or AMWEN is deasserted, the S5933 removes
its PCI bus request and gives up control of the bus.
AMREN and AMWEN are useful for Add-Ons with
external FIFOs cascaded into the S5933. For PCI
bus master write operations, the entire S5933 Add-
On to PCI FIFO and the external FIFO may be filled
before enabling bus mastering, providing a single
long burst write rather than numerous short bursts.
In some applications, the amount of data to be trans-
ferred is not known. During read operations, the
S5933, attempting to fill its PCI to Add-On FIFO, may
access up to eight memory locations beyond what is
required by the Add-On before it stops. In this situa-
tion, AMREN can be deasserted to disable PCI
reads, and then FRC# can be asserted to flush the
unwanted data from the FIFO.
11.2.3.4 FIFO Generated Add-On Interrupts
For Add-On initiated bus mastering, the S5933 may
be configured to generate interrupts to the Add-On
interface for the following situations:
– Read transfer count reaches zero
– Write transfer count reaches zero
– An error occurred during the bus master trans-
action
The interrupt is posted to the Add-On interface with
the IRQ# output. A high-to-low transition on this out-
put indicates an interrupt condition. Because there is
a single interrupt output and multiple interrupt condi-
tions, the Add-On Interrupt Control/Status Register
(AINT) must be read to determine the interrupt
source. This register is also used to clear the inter-
rupt, returning IRQ# to its high state. If mailbox inter-
rupts are also used, this must be considered in the
interrupt service routine.
11.2.3.5 8-Bit and 16-Bit FIFO Add-On Interfaces
The S5933 FIFO may also be used to transfer data
between the PCI bus and 8-bit or 16-bit Add-On inter-
faces. This can be done using FIFO advance condi-
tions or the S5933 MODE input pin.
The FIFO may be used as an 8-bit or 16-bit wide
FIFO. To use the FIFO as an 8-bit interface, the ad-
vance condition should be set for byte 0 (no data is
transferred in the upper 3 bytes). To use the FIFO as
a 16-bit interface, the advance condition should be
set for byte 1 (no data is transferred in the upper 2
bytes). This allows a simple Add-On bus interface,
but it has the disadvantage of not efficiently utilizing
the PCI bus bandwidth because the host is forced to
perform 8-bit or 16-bit accesses to the FIFO on the
PCI bus. This is the only way to communicate with an
8-bit Add-On through the FIFO without additional
logic to steer byte lanes on the Add-On data bus.
Pass-Thru mode is more suited to 8-bit Add-On inter-
faces.
Implementing a 16-bit wide FIFO is a reasonable so-
lution, but to avoid wasting PCI bus bandwidth, the
best method is to allow the PCI bus and the FIFO to
operate with 32-bit data. The S5933 can assemble or
disassemble 32-bit quantities for the Add-On inter-
face. This is possible through the MODE pin. When
MODE is low, the Add-On data bus is 32-bits. When
MODE is high, the Add-On data bus is 16-bits. When
MODE is configured for 16-bit operation, BE3# be-
comes ADR1.
With the FIFO direct access signals (RDFIFO# and
WRFIFO#), the MODE pin must reflect the actual
Add-On data bus width. With MODE = 16-bits, the
S5933 automatically takes two consecutive, 16-bit
Add-On writes to the FIFO and assembles a 32-bit
value. FIFO reads operate in the same manner. Two
consecutive Add-On reads empty the 32-bit FIFO
register. The 16-bit data bus is internally steered to
the lower and upper words of the 32-bit FIFO regis-
ter.
One consideration needs to be taken when using the
FIFO direct access signals and letting the S5933 do
byte lane steering internally. The default condition
used to advance the FIFO is byte 0. This must be
changed to byte 2 or 3. When MODE is configured
for a 16-bit Add-On bus, the first 16-bit cycle to the
FIFO always accesses the low 16-bits. If the FIFO
advance condition is left at byte 0, the FIFO ad-
vances after the first 16-bit cycle and the data in the
upper 16-bits is directed to the next FIFO location,
shifting the data.
The FRC# and FWC# inputs allow Add-On logic to
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