
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-40
ADD-ON DMA CONTROLLER DESIGN FOR THE S5933
4.0
PLD EQUATIONS
The following code is written in CUPL by Logical Devices. Pin assignments will depend on the programmable
logic device the code is programmed into. The code compiles and simulates without errors.
Name
DMA_CON;
Partno
;
Date
5/19/95;
Revision
0;
Designer
JMW;
Company
AMCC;
Assembly
;
Location
;
Device
;
/******************************************************************/
/* Add-on DMA Controller
*/
/* The PLD equations below compile and have been simulated and are*/
/* believed to be correct.
AMCC assumes no liability for errors
*/
/* made in the code or logic
*/
/*
*/
/*
*/
/******************************************************************/
/*
Allowable Target Device Types:
*/
/******************************************************************/
/**
Inputs
**/
Pin
= BPCLK
;
/* Buffered PCI Clock
*/
Pin
= RDEMPTY
;
/* PCI to Add-on FIFO Empty Indicator */
Pin
= WRFULL
;
/* Add-on to PCI FIFO Full Indicator
*/
Pin
= HLDA
;
/* CPU Hold Acknowledge
*/
Pin
= [A7..0]
;
/* Address/Data Bus 7:0
*/
Pin
= [A15..8]
;
/* Address/Data Bus 15:8
*/
Pin
= [A23..16] ;
/* Address/Data Bus 23:16
*/
Pin
= [A31..24] ;
/* Address/Data Bus 31:24
*/
Pin
= nRDY_IN
;
/* DMA Controller Ready Input
*/
Pin
= nRESET
;
/* S5933 Reset Output
*/
/**
Outputs
**/
Pin
= HOLD
;
/* CPU Hold
*/
Pin
= W_nR
;
/* Bidirectional WR/RD
*/
Pin
= nRDY_OUT
;
/* Ready Output (to CPU)
*/
Pin
= nBLAST
;
/* Last Data Phase of Burst Indicator */
Pin
= nADS
;
/* Bidirectional Address Strobe
*/
Pin
= nRDFIFO
;
/* S5933 FIFO Read Input
*/
Pin
= nWRFIFO
;
/* S5933 FIFO Write Input
*/
Pin
= BE3
;
/* Byte Enable Output 3
*/
Pin
= BE2
;
/* Byte Enable Output 2
*/
Pin
= BE1
;
/* Byte Enable Output 1
*/
Pin
= BE0
;
/* Byte Enable Output 0
*/