
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
17-3
S5933
PCI CONTROLLER
S5933
PCI CONTROLLER
A
Access Time, Serial BIOS ROM 7-9
Accesses
Asynchronous 9-3, 9-4
nv RAM 9-4
Synchronous 9-3, 9-4
Add-On
Address (ADR[6:2]) 3-8
Bus Interface 9-3
Bus Size (MODE) 3-8, 9-3
Byte Enables (BE[3:0]#) 3-8, 9-3
FIFO Port 6-4
General Control/Status Register 6-13
Incoming Mailboxes 6-4
Interrupt (IRQ#) 3-10, 9-3
Interrupt Control/Status Register 6-10
Master Transfer Count Enable 6-13
Operation Registers 6-3
Outgoing Mailboxes 6-4
Pass-Thru Address Register 6-6
Pass-Thru Data Register 6-6
Read Strobe (RD#) 3-8, 9-3
Reset (SYSRST#) 3-10, 9-3
Write Strobe (WR#) 3-8, 9-3
B
Base Address Region, Assigning 4-19
Base Address Region, I/O 4-19
Base Address Region, Memory 4-19
Base Address Region, Sizing 4-19
Base Address Registers 4-19
BIOS Initialization 15-3
BIOS, PCI 15-3
Buffered PCI Clock (BPCLK) 3-10, 9-3
Built-in Self Test (BIST) 4-18
Built-in Self Test Condition Code 6-10
Burst Order 8-4
Burst Transfers, PCI Bus 8-4
Bus Master Control/Status 5-15
Bus Master Enable 4-6
Bus Master Read Address 5-7
Bus Master Read Transfer Count 5-8
Bus Master Write Address 5-5
Bus Master Write Transfer Count 5-6
Bus Mastering
Add-On Initiated 9-7
AMREN Control 9-7
AMWEN Control 9-7
PCI Bus 8-13
C
Cache Line Size 4-15
Chaining Interrupts 15-6
Class Codes 4-11, 4-12, 4-13, 4-14
Command Register 4-6
D
Device ID 4-5
E
Expansion BIOS 7-8, 9-9
Expansion ROM Base Address 4-23, 9-9
F
Fast Back-to-Back Cycles 4-6
FIFO
8/16-Bit Add-On Interface 11-14
16-Bit Endian Conversion 11-4
32-Bit Endian Conversion 11-4
64-Bit Endian Conversion 11-5
Add-On Accesses Asynchronous 11-11
Add-On Accesses Synchronous 11-12
Add-On Initiated Bus Mastering 11-6, 11-7,
11-17
Add-On Interface 11-11
Advance Condition 11-3
Block Diagram 2-5
Bus Mastering 11-6
Byte Lane Steering 11-14
Configuration at Reset 11-15
Control Signals 9-7, 11-6, 11-13
Direct Read (RDFIFO#) 3-9, 9-7, 11-12
Direct Write (WRFIFO#) 3-9, 9-7, 11-12
DMA Transfer Address 11-7
DMA Transfer Byte Count 11-7
Endian Conversion 5-12, 11-4
Error Condition Interrupts 11-8
Flag Reset (Inputs) 9-7
INDEX