
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121  (619) 450-9333
8-10
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
8.1.5.1 Target Disconnects
There are many situations where a target may dis-
connect. Slow responding targets may disconnect to
permit more efficient (faster) devices to be accessed
while they prepare for the next data phase, or a tar-
get may disconnect if it recognizes that the next data
phase in a burst transfer is out of its address range.
A target disconnects by asserting STOP#, TRDY#,
and DEVSEL# as shown in Figures 8-10a and 8-10b.
The initiator in Figure 8-10a responds to the discon-
nect condition by deasserting FRAME# on the follow-
ing clock but does not complete the data transfer until
IRDY# is asserted. This situation can only occur
when the S5933 is a target. When the S5933 is an
initiator, IRDY# is always asserted during the data
phase (no initiator wait states). The timing diagram in
Figure 8-10b applies to the S5933 as either a target
disconnecting or an initiator with its target performing
a disconnect. The S5933 performs a target discon-
nect if a burst access is attempted to the PCI Opera-
tion Registers.
Figure 8-10b. Target Disconnect Example 2 (IRDY# asserted)
Figure 8-10a. Target Disconnect Example 1 (IRDY# deasserted)
PCI CLOCK
FRAME #
IRDY#
TRDY#
STOP#
DEVSEL#
1
2
3
DATA
TRANSFERRED
TARGET DISCONNECT
IDENTIFIED
(T)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
PCI CLOCK
FRAME #
IRDY#
TRDY#
STOP#
DEVSEL#
1
2
3
DATA
TRANSFERRED
TARGET DISCONNECT
SIGNALED, DATA TRANSFERRED
(T)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET