
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
9-2
S5933
PCI CONTROLLER
DEVICE SPECIFICATION
CONTENTS
9.
ADD-ON BUS INTERFACE ............................................................................................. 9-3
9.1 ADD-ON OPERATION REGISTER ACCESSES .................................................................................. 9-3
9.1.1 Add-On Interface Signals .......................................................................................................... 9-3
9.1.1.1
System Signals .......................................................................................................... 9-3
9.1.1.2
Register Access Signals ............................................................................................ 9-3
9.1.2 Asynchronous Register Accesses ............................................................................................. 9-4
9.1.3 Synchronous FIFO and Pass-Thru Data Register Accesses ..................................................... 9-4
9.1.4 nv Memory Accesses Through the Add-On General Control/Status Register ........................... 9-4
9.2 MAILBOX BUS INTERFACE ................................................................................................................ 9-4
9.2.1 Mailbox Interrupts ...................................................................................................................... 9-7
9.3 FIFO BUS INTERFACE ........................................................................................................................ 9-7
9.3.1 FIFO Direct Access Inputs ......................................................................................................... 9-7
9.3.2 FIFO Status Signals .................................................................................................................. 9-7
9.3.3 FIFO Control Signals ................................................................................................................. 9-7
9.4 PASS-THRU BUS INTERFACE ............................................................................................................ 9-7
9.4.1 Pass-Thru Status Indicators ...................................................................................................... 9-8
9.4.2 Pass-Thru Control Inputs ........................................................................................................... 9-8
9.5 NON-VOLATILE MEMORY INTERFACE .............................................................................................. 9-8
9.5.1 Non-Volatile Memory Interface Signals ..................................................................................... 9-8
9.5.2 Accessing Non-Volatile Memory ................................................................................................ 9-9
9.5.3 nv Memory Device Timing Requirements ................................................................................. 9-11