
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
10-9
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
Servicing an Add-On mailbox interrupt (IRQ#):
1) Identify the interrupt source(s). Multiple interrupt sources are available on the S5933. The interrupt
service routine must verify that a mailbox generated the interrupt (and not some other interrupt
source).
AINT
Bit 16
Add-On incoming mailbox interrupt indicator
AINT
Bit 17
Add-On outgoing mailbox interrupt indicator
2) Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
AMBEF
Bits 31:16
Empty Add-On outgoing mailbox bytes
AMBEF
Bits 15:0
Full Add-On incoming mailbox bytes
3) Access the mailbox. Based on the contents of AMBEF, mailboxes are read or written. Reading an
incoming mailbox byte clears the corresponding status bit in AMBEF.
AIMBx
Bits 31:0
Add-On incoming mailboxes
AOMBx
Bits 31:0
Add-On outgoing mailboxes
4) Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request.
The request is cleared by writing a ‘1’ to the appropriate bit.
AINT
Bit 16
Clear Add-On incoming mailbox interrupt
AINT
Bit 17
Clear Add-On outgoing mailbox interrupt
In both cases, step 3 involves accessing the mailbox. To allow the incoming mailbox interrupt logic to
be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the
status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the
MCSR and AGCSTS registers, but this clears all status bits, not just for a single mailbox or mailbox
byte. For outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt;
this ensures the status bits are already clear.