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參數(shù)資料
| 型號(hào)： | S5933Q/7C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 153/327頁 |
| 文件大?。?/td> | 1976K |
| 代理商： | S5933Q/7C |
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Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-9
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
APPLICATION NOTE
1.0 OVERVIEW
The AMCC S5933 PCI Controller provides add-in
cards with bus mastering capabilities on the PCI
bus. The S5933 internal FIFO is used to transfer
data between the add-on and the PCI bus as a PCI
initiator (bus master). The S5933 allows burst trans-
fers at the full PCI bandwidth.
This application note discusses how the S5933 may
be used in a PCI bus mastering (DMA) application. A
brief background of DMA as it relates to the ISA bus
is provided in Section 2. The remaining sections de-
scribe the bus master capabilities of the S5933 in-
cluding add-on hardware support and required
software support. Performance for bus mastering ap-
plications on the PCI bus is also discussed. An ex-
ample C-Language program is provided in Appendix A
to set up PCI DMA transfers with the S5933 controller.
2.0 DMA BACKGROUND
In ISA bus-based personal computers, there were
two potential bus masters: the host CPU and the
system DMA controller. There was no protocol de-
fined for alternate bus masters to gain control of the
bus and transfer data to other cards or platform
memory. Most ISA add-in cards were designed as
ISA bus slaves. The DMA controller or the CPU were
used for data transfers to and from ISA cards.
For performance reasons, some ISA add-in cards
required bus mastering capabilities. To become an
ISA bus master, a free DMA channel was utilized.
The ISA card asserted a DMA request to the 8237
DMA controller, the 82C37 asserted the HOLD input
to the CPU. When the 82C37 received the HLDA
acknowledge back from the CPU, it asserted an ac-
knowledge to the add-in card. The add-in card then
had control of the ISA bus to perform data transfers.
For this reason, bus mastering is also referred to as
DMA.
The PCI bus protocol has specific provisions to allow
bus mastering (DMA) by any device connected to
the PCI bus. If add-in cards perform their own data
transfers, the host CPU is freed to perform other
tasks (code execution, etc.). The PCI bus provides a
dedicated request (REQ#)/grant(GNT#) pair to each
PCI bus device (or card slot). These are all routed to
a central bus arbiter that determines which device
controls the PCI bus, based on a predefined priority
scheme.
3.0 S5933 ARCHITECTURE
The S5933 performs DMA (bus master) transfers on
the PCI bus through its FIFO interface. It has two,
independent FIFOs. Each FIFO is 8-deep by 32-bits
wide. One is used to transfer data from the PCI bus
to the add-on, and the other is used to transfer data
from the add-on to the PCI bus. The S5933 only
performs DMA transfers to and from memory-
mapped targets.
Each FIFO has an associated address and transfer
count register. These registers may be defined by
either the host CPU or add-on logic (configurable at
reset). Each FIFO has a programmable priority and
management scheme. Each FIFO also has the abil-
ity to generate interrupts when the transfer count ex-
pires or error conditions occur during a PCI bus
transfer.
3.1
Configuring the S5933 for DMA Transfers
A DMA (bus master) transfer may be set up by either
the host CPU, or add-on logic. This is defined for the
S5933 at reset and cannot change during operation.
Initiating a DMA transfer involves setting up the
source/destination addresses and transfer counts as
well as enabling the transfer. The FIFO relative pri-
orities and FIFO management schemes are always
programmed by the host CPU.
If an external, non-volatile boot memory is used with
the S5933, the contents of offset 45h define FIFO
operation. The following bits functions are defined:
Bit 7 Bus Master Register Access
0
Address and transfer count registers only
accessible from the add-on interface
1
Address and transfer count registers only
accessible from the PCI interface (default)
Bit 6 RDFIFO# or RD# Operation
0
Synchronous Mode — RDFIFO# and RD#
functions as enables
1
Asynchronous Mode — RDFIFO# and RD#
functions as clocks (default)
Bit 5 WRFIFO# or WR# Operation
0
Synchronous Mode — WRFIFO# and WR#
functions as enables
1
Asynchronous Mode — WRFIFO# and WR#
functions as clocks (default)
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5933QC | 制造商:AMC 功能描述:IC |
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