
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
6-6
PCI CONTROLLER
S5933
DEVICE SPECIFICATION
6.5
ADD-ON PASS-THRU ADDRESS
REGISTER (APTA)
Register Name:
Add-On Pass-Thru Address
Add-On Address Offset: 28h
Power-up value:
XXXXXXXXh
Attribute:
Read Only
Size:
32 bits
This register is employed when a response is desired
when one of the Base address decode regions (see
Section 3.11) is selected during an active PCI bus
cycle. When one of the base address decode regis-
ters 1-4 encounters a PCI bus cycle which selects
the region defined by it, this device latches that cur-
rent cycle’s active address and asserts the signal
PTATN# (Pass-Thru ATtentioN). Wait states are gen-
erated on the PCI bus until either data is transferred
or the PCI bus cycle is aborted by the initiator. (See
Section 12.2)
This register provides a method for “l(fā)ive” data (regis-
tered) transfers. Intended uses include the emulating
of other hardware as well as enabling the connection
of existing external hardware to interface to the PCI
bus through the S5933.
6.6
ADD-ON PASS-THRU DATA
REGISTER (APTD)
Register Name:
Add-On Pass-Thru Data
Add-On Address Offset: 2Ch
Power-up value:
XXXXXXXXh
Attribute:
Read/Write
Size:
32 bits
This register, along with APTA described above, is
employed when a response is desired should one of
the Base address decode regions become selected
during an active PCI bus cycle (see Section 4.11).
When one of the base address decode registers 1-4
encounters a PCI bus cycle which selects the region
defined by it, the APTA register will contain that cur-
rent cycle’s active address and the device asserts the
signal PTATN# (Pass-Thru ATentioN). Wait states
are generated on the PCI bus until this register is
read (PCI bus writes) or this register is written (PCI
bus reads).