
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
17-4
PCI CONTROLLER
S5933
Flag Reset (Software) 5-15, 6-13
Interrupts, Add-On 11-14
Location 45h 11-15
Management 5-12, 11-3, 11-7
Overview 11-3
PCI Initiated Bus Mastering 11-7, 11-16
PCI Interface, Initiator 11-8
PCI Interface, Target 11-8
PCI Reads 11-11
PCI Writes 11-11
Read Transfer Control 5-15
Read/Write Transfer Priority 11-8
Status Indicators (Outputs) 3-9, 9-7, 11-6,
11-13
Status Indicators (Software) 5-15, 6-13, 11-15
Target Disconnect 11-8
Transfer Count Interrupts 11-8
Write Transfer Control 5-15
FRAME#/IRDY# Valid Combinations 8-14
H
Header Type 4-17
I
I/O Access Enable 4-6
Initialization, S5933 7-3
Initiator Preemption 8-8
Initiator Ready (IRDY#) 3-5
Interrupt
BIST 4-18
Bus Master Error 6-10
Enabling 5-11, 6-10
Hardware, to PCI 9-7
Mailbox 5-11, 6-10
Master Abort 5-11
PCI Bus 8-16
Read Transfer Count 5-11, 6-10
Target Abort 5-11
Write Transfer Count 5-11, 6-10
x86 PC 4-25
Interrupt Control/Status Register 5-11
Interrupt Handler, PC 15-7
Interrupt Line Register 4-25
Interrupt Pin Register
4-26
L
Latency Components, Bus Mastering
Bus Acquisition 8-14
Bus Arbitration 8-13
Target Latency 8-14
Latency Timer 4-16, 8-8
Locking a Target 8-14, 8-15
M
Mailbox
8/16-Bit Add-On Interface 10-5
Add-On Interface 10-5
Block Diagrams 10-3
Bus Interface, Add-On 9-4
Empty/Full Status 5-9, 6-8, 10-4
Enabling Add-On Interrupts 10-8
Enabling PCI Interrupts 10-7
Flag Reset 5-15, 6-13, 10-4
Incoming 10-3
Interlocking Mechanism 10-3
Interrupts 9-7, 10-4, 10-7
Mailbox 4, Byte 3 9-7, 10-4
Monitoring Status 10-6
Outgoing 10-3
Overview 10-3
PCI Interrupt (Direct) 10-4
PCI Operation Registers 10-5
Reading Add-On Incoming 10-7
Reading PCI Incoming 10-6
Servicing Add-On Interrupts 10-9
Servicing PCI interrupts 10-8
Status Polling 10-6
Writing Add-On Outgoing 10-7
Writing PCI Outgoing 10-6
Master Abort 4-8, 8-9
Master-Initiated Termination 8-7
Maximum Latency Register 4-28
Memory Access Enable 4-6
Memory Addressing Limit 15-8
Memory Write/Invalidate 4-7, 4-15
Minimum Grant Register 4-27
N
Normal PCI Cycle Completion 8-7
nv RAM
Accessing 5-15, 6-13, 9-8
Block Diagram 2-7
Interface Timing 9-9, 9-11
Loading from Byte-Wide 7-3
Loading from Serial 7-4
Overview 2-7
Read Operation 9-11
Read Strobe (ERD#) 3-7