
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-60
S5933
PCI CONTROLLER
#define IN_MAILBOX_1_FULL 0x000f0000
dword amcc_op_reg_base_address;
/* Operation Register Base Address */
dword name;
/* Response to IDENTIFY command */
dword mailbox_status;
/* Mailbox Empty-Full Status */
if (read_configuration_dword(bus, device_and_function,
PCI_CS_BASE_ADDRESS_0, &amcc_op_reg_base_address)) {
/* Assume I/O base address, Mask off bits 1-0 */
amcc_op_reg_base_address &= 0xFFFC;
/* Send command via Outgoing Mailbox #1 */
outpd(amcc_op_reg_base_address + AMCC_OP_REG_OMB1, IDENTIFY_COMMAND);
/* Wait for all bytes in Incoming Mailbox to be valid */
do {
mailbox_status = inpd(amcc_op_reg_base_address + AMCC_OP_REG_MBEF);
} while((mailbox_status & IN_MAILBOX_1_FULL) != IN_MAILBOX_1_FULL);
/* Read Incoming Mailbox #1 */
name = inpd(amcc_op_reg_base_address + AMCC_OP_REG_IMB1);
/* Need to check if name matches expected response */
}
Code Segment 5
Code Segment 5 first defines a bitmask to AND with
the MBEF register to determine if all bytes of the
Incoming mailbox register are valid. The base ad-
dress of the S5933 operation registers is then ob-
tained and assumed to be an I/O address to simplify
the code. Next, a command (IDENTIFY_COMMAND)
is sent to the Outgoing Register #1. This command
is, as are all mailbox commands, vendor defined. The
Mailbox Empty-Full Status Register is then polled un-
til all bytes of the Incoming Mailbox #1 are valid.
Typically, the code will need to have a timeout loop,
as all devices will not respond to this command. Fi-
nally, the Incoming Mailbox #1 Register is read. This
value must be validated against a known return
value.
Code Segment 5 used polling to obtain the command
results. The S5933 PCI Controller also allows the
code to be interrupt-driven. The Interrupt Control-Sta-
tus Register is used to indicate to the AMCC PCI
controller which byte in an Incoming mailbox register
will cause an interrupt to be generated.
FIFO Register Transfers
The AMCC PCI Controller also has a First-In-First-
Out (FIFO) transfer feature. This allows the host com-
puter to transfer data to the PCI Device via an I/O
memory transfer. This type of transfer does make use
of the processor, so the processor performance will
be severely affected. Bus master transfers (described
later) do not use the processor for the data transfer
(other than the setup).
The I/O transfer could use a FOR loop to send/re-
ceive each byte/word/dword to the FIFO, although
this would be slow. A better method would be to use
an 80x86 processor instruction that allows for an I/O
string move. Borland C/C++ does not have a function
that incorporates these instructions, so the AMCC
PCI Library contains six functions that do. The proto-
types for these functions are shown below.
void insb(word port, void *buf, int count); /* Reads Bytes */
void insw(word port, void *buf, int count); /* Reads Words */
void insd(word port, void *buf, int count); /* Reads DWords */
void outsb(word port, void *buf, int count); /* Writes Bytes */
void outsw(word port, void *buf, int count); /* Writes Words */
void outsd(word port, void *buf, int count); /* Writes DWords */
Function Prototypes