
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
15-20
BUS MASTERING WITH THE S5933 PCI MATCHMAKER
8) Enable Bus Mastering. Once steps 1-7 are
completed, the FIFO may operate as a PCI
bus master. Read and write bus master
operation may be independently enabled or
disabled. The AMREN and AMWEN inputs
control bus master enabling for add-on
initiated bus mastering. The MCSR bus
master enable bits are ignored for add-on
initiated bus mastering.
It is recommended that bus mastering be enabled as
the last step. Some applications may choose to
leave bus mastering enabled (AMREN and AMWEN
asserted) and start transfers by writing a non-zero
value to the transfer count registers (if they are en-
abled). This works, provided the entire 26-bit transfer
count is written at once. If transfer count interrupts
are enabled, they must be enabled after the transfer
count(s) are written. If interrupts are enabled and the
transfer count is zero, an interrupt occurs immedi-
ately.
5.4
Servicing an Add-on Initiated DMA
Transfer Interrupt
If interrupts are enabled, an add-on CPU interrupt
service routine is also required. The service routine
determines the source of the interrupt and resets the
interrupt. The source of the interrupt is indicated in
the Add-on Interrupt Control Register (AINT). Typi-
cally, the interrupt service routine is used to set up
the next transfer by writing a new address and trans-
fer count value (if enabled), but some applications
may also require other actions. If read transfer or
write transfer complete interrupts are enabled, the
master/target abort interrupt is automatically en-
abled. Writing a one to these clears the correspond-
ing interrupt.
AINT
Bit 21
Master/target abort caused
interrupt
AINT
Bit 19
Read transfer complete
caused interrupt
AINT
Bit 18
Write transfer complete
caused interrupt